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CHAPTER 16 INTERRUPT FUNCTIONS
Figure 16-13. Examples of Processing When Another Interrupt Request
Is Generated During Interrupt Processing (3/3
)
Notes 1.
Low default priority
2.
High default priority
Remarks 1.
“a” to “z” in the figure are arbitrary names used to differentiate between the interrupt requests and macro
service requests.
High/low default priorities in the figure indicate the relative priority levels of the two interrupt requests.
2.
Main routine
EI
EI
EI
EI
EI
EI
Interrupt Request q
Level 3)
Interrupt
Request s
(Level 1)
Interrupt Request u
(Level 0)
Interrupt
Request v
(Level 0)
Interrupt
Request w
(Level 3)
w Macro Service
q Processingr Processing
s Processing
t Processing
u Processing
v Processing
x Processing
y Processing
z Processing
Interrupt Request x
(Level 1)
Interrupt
Request r
(Level 2)
Interrupt
Request t
(Level 0)
Interrupt
Request y
Note 1
(Level 2)
Interrupt
Request z
Note 2
(Level 2)
Multiple acknowledgment of levels 3 to 0. If
the PRSL bit of the IMC is set (1), only
macro service requests and non-maskable
interrupts generate nesting beyond this.
If the PRSL bit of the IMC is cleared (0),
level 3 interrupts can also be nested during
level 3 interrupt processing (refer to
Figure
16-15
).
Even though the interrupt enabled state is
set during processing of level 0 interrupt
request u, the interrupt request is not
acknowledged but held pending even
though its priority is 0. However, the macro
service request is acknowledged and
processed irrespective of its level and even
though there is a peding interrupt with a
higher priority level.
Pending interrupt requests y and z are
acknowledged after servicing of interrupt
request x. As interrupt requests y and z
have the same priority level, interrupt
request z which has the higher default
priority is acknowledged first, irrespective
of the order in which the interrupt requests
were generated.