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CHAPTER 21 INSTRUCTION OPERATIONS
CHAPTER 21 INSTRUCTION OPERATIONS
21.1 Legend
(1) Explanation of operand identifiers (1/2)
Identifier
Explanation
r, r’
Note 1
r1
Note 1
r2
r3
rp, rp’
Note 2
rp1
Note 2
rp2
rg, rg’
sfr
sfrp
X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7, R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15)
X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7
R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15)
V, U, T, W
AX(RP0), BC(RP1), RP2, RP3, VP(RP4), UP(RP5), DE(RP6), HL(RP7)
AX(RP0), BC(RP1), RP2, RP3
VP(RP4), UP(RP5), DE(RP6), HL(RP7)
VVP(RG4), UUP(RG5), TDE(RG6), WHL(RG7)
Special function register symbol (Refer to
Special Function Register Application Table
)
Special function register symbol (register for which 16-bit operation is possible: Refer to
Special
Function Register Application Table
)
post
Note 2
AX(RP0), BC(RP1), RP2, RP3, VP(RP4), UP(RP5)/PSW, DE(RP6), HL(RP7)
Multiple descriptions are permissible. However, UP is only used with PUSH/POP instructions, and
PSW with PUSHU/POPU instructions.
mem
[TDE], [WHL], [TDE+], [WHL+], [TDE–], [WHL–], [VVP], [UUP]: Register indirect addressing
[TDE+byte], [WHL+byte], [SP+byte], [UUP+byte], [VVP+byte]: Based addressing
imm24 [A], imm24 [B], imm24 [DE], imm24 [HL]: Indexed addressing
[TDE+A], [TDE+B], [TDE+C], [WHL+A], [WHL+B], [WHL+C],
[VVP+DE], [VVP+HL]: Based indexed addressing
mem1
All mem except [WHL+] and [WHL–]
mem2
[TDE], [WHL]
mem3
[AX], [BC], [RP2], [RP3], [VVP], [UUP], [TDE], [WHL]
Notes 1.
Setting the RSS bit to 1 enables R4 to R7 to be used as X, A, C and B, but this function should only be used
when using a 78K/III series program.
2.
Setting the RSS bit to 1 enables RP2 and RP3 to be used as AX and BC, but this function should only be used
when using a 78K/III series program.