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CHAPTER 3 SYSTEM CONTROLLER
226
Preliminary User’s Manual S14767EJ1V0UM00
Offset
Name
R/W
Access
Description
Default
D0H
D4H
D8H
DCH
E0H
E4H:
FFH
100H
104H
108H
10CH
110H
114:
11BH
11CH
120H
124H
128H
12CH
130H:
FFFH
ECCR
ERDR
MACAR1
MACAR2
MACAR3
N/A
W
R
R
R
R
----
W/H/B
W/H/B
W/H/B
W/H/B
W/H/B
----
EEPROM Command Control Register
EEPROM Read Data Register
MAC Address Register 1
MAC Address Register 2
MAC Address Register 3
Reserved
00000000H
80000000H
00000000H
00000000H
00000000H
unknown
RMMDR
RMATR
SDMDR
SDTSR
SDPTR
N/A
R/W
R/W
R/W
R/W
R/W
----
W
W
W
W
W
----
Boot ROM Mode Register
Boot ROM Access Timing Register
SDRAM Mode Register
SDRAM Type Selection Register
SDRAM Precharge Timing Register
Reserved
00000000H
00000000H
00000330H
00000000H
00000142H
unknown
SDRMR
SDRCR
MBCR
MESR
MEAR
N/A
R/W
R
R/W
RC
RC
----
W
W
W
W
W
----
SDRAM Refresh Mode Register
SDRAM Refresh Timer Count Register
Memory Bus Control Register
Memory Error Status Register
Memory Error Address Register
Reserved
00000200H
00000200H
00000000H
00000000H
00000000H
unknown
Remarks 1.
In the “R/W” field,
“W” means “writeable”
“R” means “readable”
“RC” means “read-cleared”
“----“ means “not accessible”
2.
All internal registers are 32bit word aligned register.
3.
The burst access to the internal register is prohibited.
If such burst access has been occurred, IRERR bit in NSR is set and NMI will assert to CPU.
4.
Read access to the reserved area will set the CBERR bit in the NSR register, and the dummy read
response data with the data-error bit set on SysCMD[0] is returned.
5.
Write access to the reserved area will set the CBERR bit in the NSR register, and the write data is lost.
6.
In the “Access” filed,
“W” means that Word access is valid.
“H” means that Half word access is valid.
“B” means that Byte access is valid.
7.
Write access to the read-only register cause no error, but the write data is lost.
8.
The CPU can access all internal register, but IBUS Master device cannot access them.