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CHAPTER 1 INTRODUCTION
48
Preliminary User’s Manual S14767EJ1V0UM00
Core
Offset
Register
Length
(Byte)
4
4
-
4
4
-
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
4
4
4
4
-
4
4
Name
Access by
V
R
4120A
Description
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
Ether
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
SYSCNT
DCH
E0H
E4H-12CH
130H
134H
138H-13CH
140H
144H
148H
14CH
150H
154H
158H
15CH
160H
164H
168H
16CH
170H
174H
178H
17CH
180H
184H
188H
18CH
190H
194H
198H
1C0H
1C4H
1C8H
1CCH
1D0H
1D4H
1D8H
1DCH
1E0H
1E4H
1E8H
1ECH
1F0H
1F4H
1F8H
1FCH
200H
204H
208H
20CH
210H
214H
218H
21CH
220H
224H
228H
22CH
230H
00H
04H
08H
0CH
10H
14H
18H
1CH
20H-2FH
30H
34H
38H
3CH
40H-48H
4CH
50H
En_CAR1
En_CAR2
N/A
En_CAM1
En_CAM2
N/A
En_RBYT
En_RPKT
En_RFCS
En_RMCA
En_RBCA
En_RXCF
En_RXPF
En_RXUO
En_RALN
En_RFLR
En_RCDE
En_RFCR
En_RUND
En_ROVR
En_RFRG
En_RJBR
En_R64
En_R127
En_R255
En_R511
En_R1K
En_RMAX
En_RVBT
En_TBYT
En_TPCT
En_TFCS
En_TMCA
En_TBCA
En_TUCA
En_TXPF
En_TDFR
En_TXDF
En_TSCL
En_TMCL
En_TLCL
En_TXCL
En_TNCL
En_TCSE
En_TIME
En_TXCR
En_TXFCR
En_TXDTR
En_TXSR
N/A
En_TXDPR
En_RXCR
En_RXFCR
En_RXDTR
En_RXSR
N/A
En_RXDPR
En_RXPDR
S_GMR
S_GSR
S_ISR
S_IMR
S_NSR
S_NMR
S_VER
S_IOR
N/A
S_WRCR
S_WRSR
S_PWCR
S_PWSR
N/A
S_ITCNTR
S_ITSETR
R/W
R/W
-
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
-
R/W
R/W
R/W
R
R
-
R/W
R/W
R/W
R
RC
W
R
R/W
R
R/W
-
W
R
W
R
-
R/W
R/W
Carry register 1
Carry register 2
Reserved for future use
Carry mask register 1
Carry mask register 2
Reserved for future use
Receive Byte Counter
Receive Packet Counter
Receive FCS Error Counter
Receive Multicast Packet Counter
Receive Broadcast Packet Counter
Receive Control Frame Packet Counter
Receive PAUSE Frame Packet Counter
Receive Unknown OP code Counter
Receive Alignment Error Counter
Receive Frame Length Out of Range Counter
Receive Code Error Counter
Receive False Carrier Counter
Receive Undersize Packet Counter
Receive Oversize Packet Counter
Receive Error Undersize Packet Counter
Receive Error Oversize Packet Counter
Receive 64 Byte Frame Counter
Receive 65 to 127 Byte Frame Counter
Receive 128 to 255 Byte Frame Counter
Receive 256 to 511 Byte Frame Counter
Receive 512 to 1023 Byte Frame Counter
Receive Over 1023 Byte Frame Counter
Receive Valid Byte Counter
Transmit Byte Counter
Transmit Packet Counter
Transmit CRC Error Packet Counter
Transmit Multicast Packet Counter
Transmit Broadcast Packet Counter
Transmit Unicast Packet Counter
Transmit PAUSE control Frame Counter
Transmit Single Deferral Packet Counter
Transmit Excessive Deferral Packet Counter
Transmit Single Collision Packet Counter
Transmit Multiple collision Packet Counter
Transmit Late Collision Packet Counter
Transmit Excessive Collision Packet Counter
Transmit Total Collision Counter
Transmit Carrier Sense Error Counter
Transmit Internal MAC Error Counter
Transmit Configuration Register
Transmit FIFO Control Register
Transmit Data Register
Transmit Status Register
Reserved for future use
Transmit Descriptor Register
Receive Configuration Register
Receive FIFO Control Register
Receive Data Register
Receive Status Register
Reserved for future use
Receive Descriptor Register
Receive Pool Descriptor Register
General Mode Register
General Status Register
Interrupt Status Register
Interrupt Mask Register
NMI Status Register
NMI Enable Register
Version Register
IO Port Register
Reserved
Warm Reset Control Register
Warm Reset Status Register
Power Control Register
Power Control Status Register
Reserved
IBUS Timeout Timer Control Register
IBUS Timeout Timer Set Register