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CHAPTER 2 V
R
4120A
84
Preliminary User’s Manual S14767EJ1V0UM00
2.3 MIPS16 Instruction Set
If the MIPS16 ASE (Application-Specific Extension), which is an expanded function for MIPS ISA (Instruction Set
Architecture), is used, system costs can be considerably reduced by lowering the memory capacity requirement of
embedded hardware. MIPS16 is an instruction set that uses the 16-bit instruction length, and is compatible with MIPS
I, II, III, IV, and V
executed with the V
R
4120A.
Note
instruction sets in any combination. Moreover, 32-bit instruction length binary data can be
Note
The V
R
4100 Series
currently supports the MIPS I, II, and III instruction sets.
2.3.1 Features
16-bit length instruction format
Reduces memory capacity requirements to lower overall system cost
MIPS16 instructions can be used with MIPS instruction binary
Compatibility with MIPS I, II, III, IV, and V instruction sets
Used with switching between MIPS16 instruction length mode and 32-bit MIPS instruction length mode.
Supports 8-bit, 16-bit, 32-bit, and 64-bit data formats
Provides 8 general registers and special registers
Improved code generation efficiency using special 16-bit dedicated instructions
2.3.2 Register set
Tables 2-22 and 2-23 show the MIPS16 register sets. These register sets form part of the register sets that can be
accessed in 32-bit instruction length mode. MIPS16 ASE can directly access 8 of the 32 registers that can be used in
the 32-bit instruction length mode.
In addition to these 8 general registers, the special instructions of MIPS16 ASE reference the stack pointer register
(sp), return address register (ra), condition code register (t8), and program counter (pc). sp and ra are mapped by
fixing to the general registers in the 32-bit instruction length mode.
MIPS16 has 2 move instructions that are used in addressing 32 general registers.