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CHAPTER 3 SYSTEM CONTROLLER
248
Preliminary User’s Manual S14767EJ1V0UM00
3.4.5.7 SDRAM Refresh Timer Count Register (SDRCR)
The SDRAM Refresh Timer Count Register “SDRCR” is read-only and word aligned 32bit register. SDRCR is 16bit
timer that causes an SDRAM refresh when it expires. The SDRAM refresh controller automatically reloads this free-
running timer. SDRCR is initialized to 000_0200H at reset and contains the following fields:
Bits
Field
Description
15:0
RCC
This filed shows the current value of SDRAM Refresh Timer.
31:16
Reserved
Hardwired to 0.
3.4.5.8 Memory Bus Control Register (MBCR)
The Memory Bus Control Register “MBCR” is read-write and word aligned 32bit register. MBCR is used to selects
priority for ether CPU or IBUS for memory access. The V
R
4120A can assign higher priority to CPU request for
memory than IBUS request or assign equal priority to CPU and IBUS request for memory. MBCR is initialized to 0 at
reset and contains the following fields:
Bits
Field
Description
0
BPR
Priority for memory access:
0 : SysAD(CPU) > IBUS = Refresh (default)
The memory arbiter allows the CPU to perform one memory transaction when the current word counts
of burst access from IBUS reaches each 16words or 32words.
1 : SysAD(CPU) = IBUS = Refresh
The memory arbiter doses allows the CPU to perform the memory transaction when the burst memory
access form IBUS are
31:1
Reserved
Hardwired to 0.