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參數資料
| 型號： | 2495 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit 8-/16-Channel ツヒ ADC with PGA, Easy Drive and I2C Interface |
| 中文描述： | 16位8-/16-ChannelツヒADC，帶PGA巡回賽，輕松驅動和I2C接口 |
| 文件頁數： | 15/32頁 |
| 文件大?。?/td> | 558K |
| 代理商： | 2495 |
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LTC2495
15
2495f
The LTC2495 has two registers. The output register (24 bits
long) contains the last conversion result. The input register
(16 bits long) sets the input channel, selects the temperature
sensor, rejection mode, gain and speed mode.
DATA OUTPUT FORMAT
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters the sleep state where the supply current is
reduced to 1μA. When the LTC2495 is addressed for a read
operation, it acknowledges (by pulling SDA low) and acts
as a transmitter. The master/receiver can read up to three
bytes from the LTC2495. After a complete read operation
(3 bytes), a new conversion is initiated. The device will
NAK subsequent read operations while a conversion is
being performed.
The data output stream is 24 bits long and is shifted out
on the falling edges of SCL (see Figure 3a). The first bit is
the conversion result sign bit (SIG) (see Tables 1 and 2).
This bit is high if V
IN
≥ 0 and low if V
IN
< 0 (where V
IN
corresponds to the selected input signal IN
+
– IN
–
). The
second bit is the most significant bit (MSB) of the result.
The first two bits (SIG and MSB) can be used to indicate
over and under range conditions (see Table 2). If both bits
are HIGH, the differential input voltage is equal to or above
+FS. If both bits are set low, the input voltage is below –FS.
The function of these bits is summarized in Table 2. The
16 bits following the MSB bit are the conversion result in
binary, two’s complement format. The remaining six bits
are always 0.
As long as the voltage on the selected input channels (IN
+
and IN
–
) remains between –0.3V and V
CC
+ 0.3V (absolute
maximum operating range) a conversion result is gener-
ated for any differential input voltage V
IN
from –FS = –0.5
V
REF
/Gain to +FS = 0.5 V
REF
/Gain. For differential input
voltages greater than +FS, the conversion result is clamped
to the value corresponding to +FS. For differential input
voltages below –FS, the conversion result is clamped to
the value –FS – 1LSB.
Table 2. LTC2495 Status Bits
Input Range
V
IN
≥ FS
0V ≤ V
IN
< FS
–FS ≤ V
IN
< 0V
V
IN
< –FS
Bit 23
SIG
1
1
0
0
Bit 22
MSB
1
0
1
0
APPLICATIONS INFORMATION
Table 1. Output Data Format
Differential Input Voltage
V
IN
*
V
IN
* ≥ FS**
FS** – 1LSB
0.5 FS**
0.5 FS** – 1LSB
0
–1LSB
–0.5 FS**
–0.5 FS** – 1LSB
–FS**
V
IN
* < –FS**
*The differential input voltage V
IN
= IN
+
– IN
–
. **The full-scale voltage FS = 0.5 V
REF
/Gain.
Bit 23
SIG
1
1
1
1
1
0
0
0
0
0
Bit 22
MSB
1
0
0
0
0
1
1
1
1
0
Bit 21
0
1
1
0
0
1
1
0
0
1
Bit 20
0
1
0
1
0
1
0
1
0
1
Bit 19
…
Bit 6
LSB
0
1
0
1
0
1
0
1
0
1
Bits 5-0
Always 0
000000
000000
000000
000000
000000
000000
000000
000000
000000
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
…
…
…
…
…
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