參數(shù)資料
型號: 2495
廠商: Linear Technology Corporation
英文描述: 16-Bit 8-/16-Channel ツヒ ADC with PGA, Easy Drive and I2C Interface
中文描述: 16位8-/16-ChannelツヒADC,帶PGA巡回賽,輕松驅(qū)動和I2C接口
文件頁數(shù): 4/32頁
文件大小: 558K
代理商: 2495
LTC2495
4
2495f
I
2
C INPUTS AND DIGITAL OUTPUTS
operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 3)
SYMBOL
PARAMETER
V
IH
High Level Input Voltage
V
IL
Low Level Input Voltage
V
IHA
Low Level Input Voltage for Address Pins CA0, CA1, CA2
V
ILA
High Level Input Voltage for Address Pins CA0, CA1, CA2
R
INH
Resistance from CA0, CA1, CA2 to V
CC
to Set Chip
Address Bit to 1
R
INL
Resistance from CA0, CA1, CA2 to GND to Set Chip
Address Bit to 0
R
INF
Resistance from CA0, CA1, CA2 to GND or V
CC
to Set
Chip Address Bit to Float
I
I
Digital Input Current (F
O
)
V
HYS
Hysteresis of Schmitt Trigger Inputs
V
OL
Low Level Output Voltage (SDA)
t
OF
Output Fall Time V
IH(MIN)
to V
IL(MAX)
The
denotes the specifications which apply over the full
ANALOG INPUT AND REFERENCE
temperature range, otherwise specifications are at T
A
= 25°C. (Note 3)
SYMBOL
PARAMETER
IN
+
Absolute/Common Mode IN
+
Voltage
(IN
+
Corresponds to the Selected Positive Input Channel)
IN
Absolute/Common Mode IN
Voltage
(IN
Corresponds to the Selected Negative Input Channel)
V
IN
FS
Full Scale of the Differential Input (IN
+
– IN
)
LSB
Least Significant Bit of the Output Code
REF
+
Absolute/Common Mode REF
+
Voltage
REF
Absolute/Common Mode REF
Voltage
V
REF
CS(IN
+
)
IN
+
Sampling Capacitance
CS(IN
)
IN
Sampling Capacitance
CS(V
REF
)
V
REF
Sampling Capacitance
I
DC_LEAK(IN+)
I
DC_LEAK(IN–)
I
DC_LEAK(REF+)
I
DC_LEAK(REF–)
t
OPEN
MUX Break-Before-Make
QIRR
MUX Off Isolation
The
denotes the specifications which apply over the full operating
CONDITIONS
MIN
TYP
MAX
UNITS
GND – 0.3V
V
CC
+ 0.3V
V
GND – 0.3V
V
CC
+ 0.3V
V
Input Differential Voltage Range (IN
+
– IN
)
–FS
+FS
V
V
0.5V
REF
/Gain
FS/2
16
0.1
GND
0.1
V
CC
V
V
V
REF
+
– 0.1V
V
CC
Reference Voltage Range (REF
+
– REF
)
11
11
11
1
1
1
1
50
120
pF
pF
pF
nA
nA
nA
nA
ns
dB
IN
+
DC Leakage Current
IN
DC Leakage Current
REF
+
DC Leakage Current
REF
DC Leakage Current
Sleep Mode, IN
+
= GND
Sleep Mode, IN
= GND
Sleep Mode, REF
+
= V
CC
Sleep Mode, REF
= GND
–10
–10
–100
–100
10
10
100
100
V
IN
= 2V
P-P
DC to 1.8MHz
CONDITIONS
MIN
0.7V
CC
TYP
MAX
UNITS
V
V
V
V
0.3V
CC
0.05V
CC
10
0.95V
CC
k
Ω
10
k
Ω
2
M
Ω
–10
10
μA
V
V
ns
(Note 5)
I = 3mA
Bus Load C
B
10pF to
400pF (Note 14)
0.1V
CC
≤ V
IN
≤ 0.9 V
CC
0.05V
CC
20 + 0.1C
B
0.4
250
I
IN
C
CAX
Input Leakage (SDA/SCL)
External Capacitative Load on Chip Address Pins (CA0,
CA1, CA2) for Valid Float
1
10
μA
pF
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