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參數(shù)資料
| 型號： | 25C256 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 256K 5.0V SPI Bus Serial EEPROM(4.5~5.5V,256K位,SPI總線串行EEPROM) |
| 中文描述： | 256K 5.0V SPI總線串行EEPROM（4.5?5.5V的，256K位和SPI總線串行EEPROM的） |
| 文件頁數(shù)： | 105/170頁 |
| 文件大?。?/td> | 4191K |
| 代理商： | 25C256 |
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2003 Microchip Technology Inc.
Preliminary
DS40300C-page 103
PIC16F62X
TABLE 14-9:
SUMMARY OF INTERRUPT REGISTERS
14.7
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W register and
STATUS register). This will have to be implemented in
software.
Example 14-2 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in a common memory location (i.e., W_TEMP is
defined at 0x70 in Bank 0 and is therefore, accessible
at 0xF0, 0x17 and 0xIFD). The Example 14-2:
Stores the W register
Stores the STATUS register
Executes the ISR code
Restores the STATUS (and bank select bit
register)
Restores the W register
EXAMPLE 14-2:
SAVING THE STATUS
AND W REGISTERS IN
RAM
14.8
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the ER
oscillator of the CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1 and OSC2 pins
of the device has been stopped, for example, by
execution of a
SLEEP
instruction. During normal
operation, a WDT timeout generates a device RESET.
If the device is in SLEEP mode, a WDT timeout causes
the device to wake-up and continue with normal opera-
tion. The WDT can be permanently disabled by
programming the configuration bit WDTE as clear
(Section 14.1).
14.8.1
WDT PERIOD
The WDT has a nominal timeout period of 18 ms (with
no prescaler). The timeout periods vary with tempera-
ture, V
DD
and process variations from part to part (see
DC specs). If longer timeout periods are desired, a
postscaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, timeout periods up to 2.3
seconds can be realized.
The
CLRWDT
and
SLEEP
instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer timeout.
14.8.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (V
DD
= Min., Temperature = Max., max.
WDT prescaler), it may take several seconds before a
WDT timeout occurs.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Value on all
other
RESETS
(1)
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 -000
0000 -000
0000 000u
0000 -000
0000 -000
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF TMR1IF
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE
Note
1:
Other (non Power-up) Resets include MCLR Reset, Brown-out Detect Reset and Watchdog Timer Reset during normal
operation.
MOVWF
W_TEMP
;copy W to temp register,
could be in either bank
SWAPF
STATUS,W
;swap status to be saved
into W
BCF
STATUS,RP0
;change to bank 0 regardless
of current bank
MOVWF
STATUS_TEMP
;save status to bank 0
register
:
: (ISR)
:
SWAPF
STATUS_TEMP,W
;swap STATUS_TEMP register
into W, sets bank to origi-
nal
state
MOVWF
STATUS
;move W into STATUS register
SWAPF
W_TEMP,F
;swap W_TEMP
SWAPF
W_TEMP,W
;swap W_TEMP into W
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