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參數(shù)資料
| 型號： | 25C256 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 256K 5.0V SPI Bus Serial EEPROM(4.5~5.5V,256K位,SPI總線串行EEPROM) |
| 中文描述： | 256K 5.0V SPI總線串行EEPROM（4.5?5.5V的，256K位和SPI總線串行EEPROM的） |
| 文件頁數(shù)： | 82/170頁 |
| 文件大?。?/td> | 4191K |
| 代理商： | 25C256 |
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PIC16F62X
DS40300C-page 80
Preliminary
2003 Microchip Technology Inc.
12.3
USART Function
The USART function is similar to that on the
PIC16C74B, which includes the BRGH = 1 fix.
12.3.1
USART 9-BIT RECEIVER WITH
ADDRESS DETECT
When the RX9 bit is set in the RCSTA register, 9 bits
are received and the ninth bit is placed in the RX9D bit
of the RCSTA register. The USART module has a
special provision for multiprocessor communication.
Multiprocessor communication is enabled by setting
the ADEN bit (RCSTA<3>) along with the RX9 bit. The
port is now programmed so when the last bit is
received, the contents of the Receive Shift Register
(RSR) are transferred to the receive buffer. The ninth
bit of the RSR (RSR<8>) is transferred to RX9D, and
the receive interrupt is set if, and only, if RSR<8> = 1.
This feature can be used in a multiprocessor system as
follows:
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
byte that identifies the target slave. An address byte is
identified by setting the ninth bit (RSR<8>) to a '1'
(instead of a '0' for a data byte). If the ADEN and RX9
bits are set in the slave’s RCSTA register, enabling mul-
tiprocessor communication, all data bytes will be
ignored. However, if the ninth received bit is equal to a
‘1’, indicating that the received byte is an address, the
slave will be interrupted and the contents of the RSR
register will be transferred into the receive buffer. This
allows the slave to be interrupted only by addresses, so
that the slave can examine the received byte to see if it
is being addressed. The addressed slave will then clear
its ADEN bit and prepare to receive data bytes from the
master.
When ADEN is enabled (='1'), all data bytes are
ignored. Following the STOP bit, the data will not be
loaded into the receive buffer, and no interrupt will
occur. If another byte is shifted into the RSR register,
the previous data byte will be lost.
The ADEN bit will only take effect when the receiver is
configured in 9-bit mode (RX9 = '1'). When ADEN is
disabled (='0'), all data bytes are received and the 9th
bit can be used as the PARITY bit.
The USART Receive Block Diagram is shown in
Figure 12-8.
Reception
(RCSTA<4>).
is
enabled
by
setting
bit
CREN
12.3.1.1
Setting up 9-bit mode with Address
Detect
Steps to follow when setting up an Asynchronous or
Synchronous Reception with Address Detect Enabled:
1.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH.
2.
Enable asynchronous or synchronous commu-
nication by setting or clearing bit SYNC and
setting bit SPEN.
3.
If interrupts are desired, then set enable bit
RCIE.
4.
Set bit RX9 to enable 9-bit reception.
5.
Set ADEN to enable address detect.
6.
Enable the reception by setting enable bit CREN
or SREN.
7.
Flag bit RCIF will be set when reception is
complete, and an interrupt will be generated if
enable bit RCIE was set.
8.
Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
9.
If any error occurred, clear the error by clearing
enable bit CREN if it was already set.
10. If the device has been addressed (RSR<8> = 1
with address match enabled), clear the ADEN
and RCIF bits to allow data bytes and address
bytes to be read into the receive buffer and
interrupt the CPU.
TABLE 12-8:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
RESETS
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF
0000 -000
FERR
OERR
RX9D
0000 -000
0000 -00x
0000 0000
0000 -000
0000 -010
0000 0000
18h
RCSTA
SPEN
RX9
SREN
CREN
ADEN
0000 -00x
0000 0000
1Ah
RCREG
RX7
RX6
RX5
RX4
RX3
RX2
CCP1IE TMR2IE TMR1IE
0000 -000
BRGH
TRMT
RX1
RX0
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
TX9D
0000 -010
0000 0000
99h
Legend:
x
= unknown,
-
= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
SPBRG Baud Rate Generator Register
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