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參數(shù)資料
| 型號： | 25C256 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 256K 5.0V SPI Bus Serial EEPROM(4.5~5.5V,256K位,SPI總線串行EEPROM) |
| 中文描述： | 256K 5.0V SPI總線串行EEPROM（4.5?5.5V的，256K位和SPI總線串行EEPROM的） |
| 文件頁數(shù)： | 107/170頁 |
| 文件大?。?/td> | 4191K |
| 代理商： | 25C256 |
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2003 Microchip Technology Inc.
Preliminary
DS40300C-page 105
PIC16F62X
14.9.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
External RESET input on MCLR pin
2.
Watchdog Timer Wake-up (if WDT was enabled)
3.
Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
The first event will cause a device RESET. The two
latter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
PD bit, which is set on power-up is cleared when
SLEEP is invoked. TO bit is cleared if WDT Wake-up
occurred.
When the
SLEEP
instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to
wake-up
through
an
interrupt
event,
the
corresponding interrupt enable bit must be set
(enabled). Wake-up is regardless of the state of the
GIE bit. If the GIE bit is clear (disabled), the device con-
tinues execution at the instruction after the
SLEEP
instruction. If the GIE bit is set (enabled), the device
executes the instruction after the
SLEEP
instruction
and then branches to the interrupt address (0004h). In
cases where the execution of the instruction following
SLEEP
is not desirable, the user should have an
NOP
after the
SLEEP
instruction.
The WDT is cleared when the device wakes-up from
SLEEP, regardless of the source of wake-up.
FIGURE 14-17:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
14.10 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
14.11 User ID Locations
Four memory locations (2000h-2003h) are designated
as user ID locations where the user can store
checksum or other code-identification numbers. These
locations are not accessible during normal execution
but are readable and writable during program/verify.
Only the Least Significant 4 bits of the user ID locations
are used.
Note:
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP
instruction is completely executed.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC
PC+1
PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
(
Note 2
)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h)
Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2
0004h
0005h
Dummy cycle
Tost
(2)
PC+2
Note
1:
2:
3:
XT, HS or LP Oscillator mode assumed.
T
OST
= 1024T
OSC
(drawing not to scale). Approximately 1
μ
s delay will be there for ER Osc mode.
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue
in-line.
CLKOUT is not available in these Osc modes, but shown here for timing reference.
4:
Note:
The entire data EEPROM and FLASH
program memory will be erased when the
code protection is turned off. The INTRC
calibration data is not erased.
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