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參數(shù)資料
| 型號： | 25C256 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 256K 5.0V SPI Bus Serial EEPROM(4.5~5.5V,256K位,SPI總線串行EEPROM) |
| 中文描述： | 256K 5.0V SPI總線串行EEPROM（4.5?5.5V的，256K位和SPI總線串行EEPROM的） |
| 文件頁數(shù)： | 98/170頁 |
| 文件大?。?/td> | 4191K |
| 代理商： | 25C256 |
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PIC16F62X
DS40300C-page 96
Preliminary
2003 Microchip Technology Inc.
14.5
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Detect
(BOD)
14.5.1
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in RESET until
V
DD
has reached a high enough level for proper
operation. To take advantage of the POR, just tie the
MCLR pin through a resistor to V
DD
. This will eliminate
external RC components usually needed to create
Power-on Reset. A maximum rise time for V
DD
is
required. See Electrical Specifications for details.
The POR circuit does not produce an internal RESET
when V
DD
declines.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating
conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting”.
14.5.2
POWER-UP TIMER (PWRT)
The PWRT provides a fixed 72 ms (nominal) timeout
on power-up only, from POR or Brown-out Detect
Reset. The PWRT operates on an internal RC oscilla-
tor. The chip is kept in RESET as long as PWRT is
active. The PWRT delay allows the V
DD
to rise to an
acceptable level. A configuration bit, PWRTE can
disable (if set) or enable (if cleared or programmed) the
PWRT. The PWRT should always be enabled when
Brown-out Detect Reset is enabled.
The Power-Up Time delay will vary from chip to chip
and due to V
DD
, temperature and process variation.
See DC parameters for details.
14.5.3
OSCILLATOR START-UP TIMER
(OST)
The OST provides a 1024 oscillator cycle (from OSC1
input) delay after the PWRT delay is over. This ensures
that the crystal oscillator or resonator has started and
stabilized.
The OST timeout is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
14.5.4
BROWN-OUT DETECT (BOD)
RESET
The PIC16F62X members have on-chip BOD circuitry.
A configuration bit, BODEN, can disable (if clear/
programmed) or enable (if set) the BOD Reset circuitry.
If V
DD
falls below V
BOD
for longer than T
BOD
, the
brown-out situation will RESET the chip. A RESET is
not guaranteed to occur if V
DD
falls below V
BOD
for
shorter than T
BOD
. V
BOD
and T
BOD
are defined in
Table 17-1 and Table 17-6, respectively.
On any RESET (Power-on, Brown-out, Watchdog, etc.)
the chip will remain in RESET until V
DD
rises above
V
BOD
. The Power-up Timer will now be invoked and will
keep the chip in RESET an additional 72 ms.
If V
DD
drops below V
BOD
while the Power-up Timer is
running, the chip will go back into a Brown-out Detect
Reset and the Power-up Timer will be re-initialized.
Once V
DD
rises above V
BOD
, the Power-Up Timer will
execute a 72 ms RESET. The Power-up Timer should
always be enabled when Brown-out Detect is enabled.
Figure 14-7 shows typical Brown-out situations.
FIGURE 14-7:
BROWN-OUT SITUATIONS
72 MS
V
BOD
V
DD
INTERNAL
RESET
V
BOD
V
DD
INTERNAL
RESET
72 MS
<72 MS
72 MS
V
BOD
V
DD
INTERNAL
RESET
≥
T
BOD
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