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參數(shù)資料
| 型號： | 28F004SC |
| 廠商： | Intel Corp. |
| 英文描述： | BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| 中文描述： | 字節(jié)寬SmartVoltage FlashFile Memory系列4，8和16兆比特 |
| 文件頁數(shù)： | 16/41頁 |
| 文件大小： | 703K |
| 代理商： | 28F004SC |
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BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY
E
16
PRELIMINARY
4.1
Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to read
array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, program, or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or
Program Suspend command. The Read Array
command functions independently of the V
PP
voltage and RP# can be V
IH
or V
HH
.
4.2
Read Identifier Codes
Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Figure 6 retrieve the manufacturer, device, block
lock configuration and master lock configuration
codes (see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read
Identifier
Codes
independently of the V
voltage and RP# can be
V
IH
or V
HH
. Following the Read Identifier Codes
command, the subsequent information can be read.
command
functions
Table 4. Identifier Codes
Code
Address
000000
000001
000001
000001
XX
0002
(1)
Data
89
A7
A6
AA
Manufacturer Code
4-Mbit
8-Mbit
16-Mbit
Device Code
Block Lock Configuration
Block Is Unlocked
Block Is Locked
Reserved for Future Use
Master Lock Configuration
Device Is Unlocked
Device Is Locked
Reserved for Future Use
NOTE:
1.
X selects the specific block lock configuration code to
be read. See Figure 5 for the device identifier code
memory map.
DQ
0
= 0
DQ
0
= 1
DQ
1
–7
000003
DQ
0
= 0
DQ
0
= 1
DQ
1–7
4.3
Read Status Register
Command
The status register may be read to determine when
a block erase, program, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs first. OE# or CE# must
toggle to V
IH
to update the status register latch. The
Read
Status
Register
independently of the V
PP
voltage. RP# can be V
IH
or V
HH
.
command
functions
4.4
Clear Status Register
Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to
“1”s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V
voltage. RP# can
be V
IH
or V
HH
. This command is not functional
during block erase or program suspend modes.
4.5
Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
written first, followed by a block erase confirm. This
command sequence requires appropriate se-
quencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register
data when read (see Figure 7). The CPU can detect
block erase completion by analyzing the RY/BY#
pin or status register bit SR.7.
相關PDF資料 |
PDF描述 |
|---|---|
| 28F008B3 | SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| 28F008C3 | 3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| 28F008SA | 8-MBIT (1-MBIT x 8) FlashFileTM MEMORY |
| 28F008SA-L | 8-MBIT (1 MBIT x 8) FLASHFILETM MEMORY |
| 28F008S3 | 3 V FlashFile Memory(3V閃速存儲器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 28F008B3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| 28F008BE-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-MBIT (512K X 16. 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 28F008BV-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Boot Flash |
| 28F008C3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| 28F008S3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Byte-Wide Smart 3 Flashfile Memory Family 4 8 and |
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