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參數(shù)資料
| 型號： | 28F004SC |
| 廠商： | Intel Corp. |
| 英文描述： | BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
| 中文描述： | 字節(jié)寬SmartVoltage FlashFile Memory系列4，8和16兆比特 |
| 文件頁數(shù)： | 27/41頁 |
| 文件大?。?/td> | 703K |
| 代理商： | 28F004SC |
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E
5.0
BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY
27
PRELIMINARY
DESIGN CONSIDERATIONS
5.1
Three-Line Output Control
Intel provides three control inputs to accommodate
multiple memory connections: CE#, OE#, and RP#.
Three-line control provides for:
a.
b.
Lowest possible memory power dissipation.
Data bus contention avoidance.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while de-
selected memory devices are in standby mode.
RP# should be connected to
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
the
system
5.2
RY/BY# Hardware Detection
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase program
and lock-bit configuration completion. This output
can be directly connected to an interrupt input of
the system CPU. RY/BY# transitions low when the
WSM is busy and returns to V
when it is finished
executing the internal algorithm. During suspend
and deep power-down modes, RY/BY# remains at
V
OH
.
5.3
Power Supply Decoupling
Flash memory power switching characteristics
require
careful
device
designers are interested in three supply current
issues: standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Two-line control and proper
decoupling
capacitor
selection
transient voltage peaks. Each device should have a
0.1 μF ceramic capacitor connected between its
V
CC
and GND and between its V
PP
and GND.
These high-frequency, low-inductance capacitors
should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7 μF
electrolytic capacitor should be placed at the array’s
power supply connection between V
and GND.
The bulk capacitor will overcome voltage slumps
caused by PC board trace inductance.
decoupling.
System
will
suppress
5.4
V
PP
Trace on Printed Circuit
Boards
Updating flash memories that reside in the target
system requires that the printed circuit board
designer pay attention to the V
power supply
trace. The V
pin supplies the memory cell current
for byte writing and block erasing. Use similar trace
widths and layout considerations given to the V
power bus. Adequate V
PP
supply traces and
decoupling will decrease V
PP
voltage spikes and
overshoots.
5.5
V
CC
, V
PP
, RP# Transitions
Block erase, program and lock-bit configuration are
not guaranteed if V
PP
or V
CC
fall outside of a valid
voltage
range
(V
CC2
RP#
≠
V
IH
or V
HH
. If V
error is detected, status
register bit SR.3 is set to “1” along with SR.4 or
SR.5, depending on the attempted operation. If RP#
transitions to V
during block erase, program, or
lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation
will abort and the device will enter deep power-
down. The aborted operation may leave data
partially altered. Therefore, the command sequence
must be repeated after normal operation is
restored.
and
V
PPH1/2
)
or
5.6
Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, byte writing, or lock-bit
configuration during power transitions. Upon power-
up, the device is indifferent as to which power
supply (V
or V
) powers-up first. Internal
circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious
writes for V
CC
voltages above V
LKO
when V
PP
is
active. Since both WE# and CE# must be low for a
command write, driving either input signal to V
will
inhibit writes. The CUI’s two-step command
sequence architecture provides an added level of
protection against data alteration.
In-system block lock and unlock renders additional
protection during power-up by prohibiting block
erase and program operations. The device is
disabled while RP# = V
IL
regardless of its control
inputs state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F008B3 | SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| 28F008C3 | 3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| 28F008SA | 8-MBIT (1-MBIT x 8) FlashFileTM MEMORY |
| 28F008SA-L | 8-MBIT (1 MBIT x 8) FLASHFILETM MEMORY |
| 28F008S3 | 3 V FlashFile Memory(3V閃速存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F008B3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
| 28F008BE-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-MBIT (512K X 16. 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 28F008BV-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Boot Flash |
| 28F008C3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| 28F008S3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Byte-Wide Smart 3 Flashfile Memory Family 4 8 and |
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