參數(shù)資料
型號(hào): 28F016SA
廠商: Intel Corp.
英文描述: 16-Mbit(1 Mbit x 16, 2 Mbit x 8) FlashFile Memory(16-M位(1 M位 x 16, 2 M位 x 8) FlashFile存儲(chǔ)器)
中文描述: 16兆位(1兆位× 16,2兆位× 8)FlashFile內(nèi)存(16米位(1米位× 16,2米位× 8)FlashFile存儲(chǔ)器)
文件頁數(shù): 45/55頁
文件大?。?/td> 849K
代理商: 28F016SA
E
28F016SA
45
SEE NEW DESIGN RECOMMENDATIONS
V
V
WE# (W)
OE# (G)
RP# (P)
VPP
CEx#(E)
(V)
DEEP
POWER-DOWN
IH
IL
V
V
IH
IL
V
V
IH
IL
ADDRESSES (A)
tAVAV
t
EHAX
t
EHWH
WLEL
t
tEHDX
EHEL
t
V
V
IH
IL
tELEH
tDVEH
VIH
IL
V
VIH
V
IL
PHEL
t
HIGH Z
IN
D
D
IN
IN
A
tQVVL
D
IN
IL
V
IH
V
PPH
V
PPL
V
tVPEH
READ EXTENDED
STATUS REGISTER DATA
DATA (D/Q)
t
EHQV1,2
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
AUTOMATED DATA-WRITE
OR ERASE DELAY
V
V
RY/BY# (R)
t
EHRL
OH
OL
V
V
IH
IL
ADDRESSES (A)
IN
A
READ COMPATIBLE
STATUS REGISTER DATA
DIN
WRITE READ EXTENDED
REGISTER COMMAND
A=RA
NOTE 1
NOTE 2
NOTE 3
NOTE 4
DOUT
AVEH
t
tRHPL
t
GHEL
NOTE 5
tAVAV
t
EHAX
AVEH
t
t
EHGL
0489_15
NOTES:
1.
2.
3.
4.
5.
This address string depicts data program/block erase cycles with corresponding verification via ESRD.
This address string depicts data program/block erase cycles with corresponding verification via CSRD.
This cycle is invalid when using CSRD for verification during data program/block erase operations.
CE
X
# is defined as the latter of CE
0
# or CE
1
# going low or the first of CE
0
# or CE
1
# going high.
RP# low transition is only to show t
RHPL
; not valid for above read and program cycles.
Figure 16. Alternate AC Waveforms for Command Write Operations
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