參數(shù)資料
型號(hào)： 405GP
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 405GP Embedded Processor
中文描述： 405GP的Power PC嵌入式處理器
文件頁(yè)數(shù)： 3/59頁(yè)
文件大?。?/td> 782K
代理商： 405GP
405GP – Power PC 405GP Embedded Processor
AMCC
11
Revision 2.03 – September 7, 2007
Data Sheet
Peripheral Device pacing with external “Ready”
External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
DMA Controller
Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
- Buffered memory to peripheral transfers
Four channels
Scatter/gather capability for programming multiple DMA operations
8-, 16-, 32-bit peripheral support (OPB and external)
32-bit addressing
Address increment or decrement
Internal 32-byte data buffering capability
Supports internal and external peripherals
Support for memory mapped peripherals
Support for peripherals running on slower frequency buses
Serial Interface
One 8-pin UART and one 4-pin UART interface provided
Selectable internal or external serial clock to allow a wide range of baud rates
Register compatibility with NS16550 register set
Complete status reporting capability
Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
Fully programmable serial-interface characteristics
Supports DMA using internal DMA engine
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