參數(shù)資料
型號(hào)： 405GP
廠(chǎng)商： Applied Micro Circuits Corp.
英文描述： Power PC 405GP Embedded Processor
中文描述： 405GP的Power PC嵌入式處理器
文件頁(yè)數(shù)： 36/59頁(yè)
文件大小： 782K
代理商： 405GP
405GP – Power PC 405GP Embedded Processor
AMCC
41
Revision 2.03 – September 7, 2007
Data Sheet
GPIO1[TS1E]
GPIO2[TS2E]
General Purpose I/O
or
Even Trace execution status. To access this function, software must
toggle a DCR bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 6
GPIO3[TS1O]
General Purpose I/O
or
Odd Trace execution status. To access this function, software must
toggle a DCR bit.
I/O[O]
5V tolerant
3.3V LVTTL
1
GPIO4[TS2O]
General Purpose I/O
or
Odd Trace execution status. To access this function, software must
toggle a DCR bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 6
GPIO5:8[TS3:6]
General Purpose I/O
or
Trace status. To access this function, software must toggle a DCR
bit.
I/O[O]
5V tolerant
3.3V LVTTL
1
GPIO9[TrcClk]
General Purpose I/O
or
Trace interface clock. A toggling signal that is always half of the CPU
core frequency. To access this function, software must toggle a DCR
bit.
I/O[O]
5V tolerant
3.3V LVTTL
1
TestEn
Test Enable. Used only for manufacturing tests. Pull down for normal
operation.
I
2.5V CMOS
w/pull-down
RcvrInh
Receiver Inhibit. Used only for manufacturing tests. Pull up for normal
operation.
I
5V tolerant
3.3V LVTTL
2
DrvrInh1:2
Driver Inhibit 1 and 2. Used only for manufacturing tests. Pull up for
normal operation.
I
5V tolerant
3.3V LVTTL
2
TmrClk
An external clock input that can be used to clock the timers in the
CPU core.
I
5V tolerant
3.3V LVTTL
1
Trace Interface
[TS1E]GPIO1
[TS2E]GPIO2
Even Trace execution status. To access this function, software must
toggle a DCR bit
or
General Purpose I/O.
O[I/O]
5V tolerant
3.3V LVTTL
1, 6
[TS1O]GPIO3
Odd Trace execution status. To access this function, software must
toggle a DCR bit
or
General Purpose I/O.
O[I/O]
5V tolerant
3.3V LVTTL
1
[TS2O]GPIO4
Odd Trace execution status. To access this function, software must
toggle a DCR bit
or
General Purpose I/O.
O[I/O]
5V tolerant
3.3V LVTTL
1, 6
Signal Functional Description (Part 7 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 34.
Signal Name
Description
I/O
Type
Notes
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