參數(shù)資料
型號： 405GP
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 405GP Embedded Processor
中文描述： 405GP的Power PC嵌入式處理器
文件頁數(shù)： 4/59頁
文件大?。?/td> 782K
代理商： 405GP
405GP – Power PC 405GP Embedded Processor
12
AMCC
Revision 2.03 – September 7, 2007
Data Sheet
IIC Bus Interface
Compliant with Philips Semiconductors I2C Specification, dated 1995
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Supports fixed VDD IIC interface
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Provides full management of all IIC bus protocol
Programmable error recovery
General Purpose IO (GPIO) Controller
Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master
accesses
23 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities
acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with:
- 7 of 8 chip selects
- All seven external interrupts
- All nine instruction trace pins
Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, three-
stated if output bit is 1)
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