Clock Generator Module (CGM)
Technical Data
MC68HC08AZ32A — Rev 1.0
142
Clock Generator Module (CGM)
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MOTOROLA
Correct selection of filter capacitor, C
F
(see
Choosing a Filter
Capacitor
on page 141).
Room temperature operation
Negligible external leakage on CGMXFC
Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K
acq
is the K factor when the PLL is configured in acquisition mode, and
K
trk
is the K factor when the PLL is configured in tracking mode. (See
Acquisition and Tracking Modes
on page 123).
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See
Manual
and Automatic PLL Bandwidth Modes
on page 123). A certain
number of clock cycles, n
ACQ
, is required to ascertain that the PLL is
within the tracking mode entry tolerance,
TRK
, before exiting acquisition
mode. A certain number of clock cycles, n
TRK
, is required to ascertain
that the PLL is within the lock mode entry tolerance,
Lock
. Therefore, the
acquisition time, t
ACQ
, is an integer multiple of n
ACQ
/f
CGMRDV
, and the
acquisition to lock time, t
AL
, is an integer multiple of n
TRK
/f
CGMRDV
. Also,
since the average frequency over the entire measurement period must
be within the specified tolerance, the total time usually is longer than
t
Lock
as calculated above.
t
acq
V
f
CGMRDV
-------------------
8
K
ACQ
------------
=
t
al
V
f
CGMRDV
-------------------
4
K
TRK
-----------
=
t
Lock
t
ACQ
t
AL
+
=
F
Freescale Semiconductor, Inc.
n
.