Serial Peripheral Interface (SPI)
Transmission Formats
MC68HC08AZ32A — Rev 1.0
Technical Data
MOTOROLA
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
241
Figure 16-8. Clearing SPRF When OVRF Interrupt is Not Enabled
16.6.7 Mode Fault Error
For the MODF flag to be set, the mode fault error enable bit (MODFEN)
must be set. Clearing the MODFEN bit does not clear the MODF flag but
does prevent MODF from being set again after MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF
interrupts share the same CPU interrupt vector. MODF and OVRF can
generate a receiver/error CPU interrupt request. See
Figure 16-9
. It is
not possible to enable only MODF or OVRF to generate a receiver/error
CPU interrupt request. However, leaving MODFEN low prevents MODF
from being set.
READ SPDR
READ SPSCR
OVRF
SPRF
BYTE 1
BYTE 2
BYTE 3
BYTE 4
1
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
BYTE 4 SETS SPRF BIT.
CPU READS SPSCR.
CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
10
11
12
13
14
SPI RECEIVE
COMPLETE
10
11
12
13
14
F
Freescale Semiconductor, Inc.
n
.