Central Processor Unit (CPU)
Instruction Set Summary
MC68HC08AZ32A — Rev 1.0
Technical Data
MOTOROLA
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
91
ORA #
opr
ORA
opr
ORA
opr
ORA
opr
,X
ORA
opr
,X
ORA ,X
ORA
opr
,SP
ORA
opr
,SP
Inclusive OR A and M
A
←
(A) | (M)
0 – –
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
9E
EA
9E
DA
ii
dd
hh
ll
ee
ff
ff
ff
ee
ff
2
3
4
4
3
2
4
5
PSHA
Push A onto Stack
Push (A); SP
←
(SP
) –
1
– – – – – – INH
87
2
PSHH
Push H onto Stack
Push (H)
;
SP
←
(SP
) –
1
– – – – – – INH
8B
2
PSHX
Push X onto Stack
Push (X)
;
SP
←
(SP
) –
1
– – – – – – INH
89
2
PULA
Pull A from Stack
SP
←
(SP +
1); Pull
(
A
)
– – – – – – INH
86
2
PULH
Pull H from Stack
SP
←
(SP +
1); Pull
(
H
)
– – – – – – INH
8A
2
PULX
Pull X from Stack
SP
←
(SP +
1); Pull
(
X
)
– – – – – – INH
88
2
ROL
opr
ROLA
ROLX
ROL
opr
,X
ROL ,X
ROL
opr
,SP
Rotate Left through Carry
– –
DIR
INH
INH
IX1
IX
SP1
39
49
59
69
79
9E
69
dd
ff
ff
4
1
1
4
3
5
ROR
opr
RORA
RORX
ROR
opr
,X
ROR ,X
ROR
opr
,SP
Rotate Right through Carry
– –
DIR
INH
INH
IX1
IX
SP1
36
46
56
66
76
9E
66
dd
ff
ff
4
1
1
4
3
5
RSP
Reset Stack Pointer
SP
←
$FF
– – – – – – INH
9C
1
RTI
Return from Interrupt
SP
←
(SP) + 1; Pull (CCR)
SP
←
(SP) + 1; Pull (A)
SP
←
(SP) + 1; Pull (X)
SP
←
(SP) + 1; Pull (PCH)
SP
←
(SP) + 1; Pull (PCL)
INH
80
7
RTS
Return from Subroutine
SP
←
SP + 1
;
Pull
(
PCH)
SP
←
SP + 1; Pull (PCL)
– – – – – – INH
81
4
SBC #
opr
SBC
opr
SBC
opr
SBC
opr
,X
SBC
opr
,X
SBC ,X
SBC
opr
,SP
SBC
opr
,SP
Subtract with Carry
A
←
(A) – (M) – (C)
– –
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9E
E2
9E
D2
ii
dd
hh
ll
ee
ff
ff
ff
ee
ff
2
3
4
4
3
2
4
5
SEC
Set Carry Bit
C
←
1
– – – – – 1 INH
99
1
Table 6-1. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
A
M
O
O
C
V H I N Z C
C
b0
b7
b0
b7
C
F
Freescale Semiconductor, Inc.
n
.