Monitor ROM (MON)
Technical Data
MC68HC08AZ32A — Rev 1.0
158
Monitor ROM (MON)
MOTOROLA
11.4.1 Entering monitor mode
Table 11-1
shows the pin conditions for entering monitor mode.
Enter monitor mode by either
Executing a software interrupt instruction (SWI) or
Applying a ‘0’ and then a ‘1’ to the RST pin.
Once out of reset, the MCU waits for the host to send eight security bytes
(see
Security
on page 164). After the security bytes, the MCU sends a
break signal (10 consecutive ‘0’s) to the host computer, indicating that it
is ready to receive a command.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as V
HI
(see
Electrical Specifications
on page 423), is applied to either the IRQ pin
or the RST pin. See
System Integration Module (SIM)
on page 95 for
more information on modes of operation.
NOTE:
Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Table 11-1. Mode Selection
I
P
P
P
P
Mode
CGMOUT
Bus
Frequency
V
HI
(1)
1
0
1
1
Monitor
or
V
HI
(1)
1
0
1
0
Monitor
CGMXCLK
1. For V
HI
,
5.0 Volt DC Electrical Characteristics
on page 426, and
Maximum Ratings
on page 424.
CG2
CG2
CG2
2
CGMOUT
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.