參數(shù)資料
型號(hào)： 6PAIC3106IRGZRQ1
廠商： Texas Instruments
文件頁(yè)數(shù)： 23/103頁(yè)
文件大?。?/td> 0K
描述： IC AUDIO CODEC STEREO 48-QFN
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 立體聲音頻
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 102（差分），92 / 95（單端）
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 91 / 99（差分），91 / 92（單端）
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.1 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 48-VQFN 裸露焊盤(pán)（7x7）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 1077 (CN2011-ZH PDF)
其它名稱(chēng)： 296-25253-6
BCLK
WCLK
0
T0152-01
1/fs
LSB
LSB MSB
MSB
LeftChannel
RightChannel
1
2
SDIN/SDOUT
n–1
n–2
n–3
n–4
n–2
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
DSP MODE
In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and
immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.
Figure 24. DSP Serial Bus Mode Operation
TDM DATA TRANSFER
Time-division multiplexed data transfer can be realized in any of the above transfer modes if the 256-clock bit
clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By
changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the
serial data output driver (DOUT) can also be programmed to 3-state during all bit clocks except when valid data
is being put onto the bus. This allows other codecs to be programmed with different offsets and to drive their
data onto the same DOUT line, just in a different slot. For incoming data, the codec simply ignores data on the
bus except where it is expected based on the programmed offset.
Note that the location of the data when an offset is programmed is different, depending on what transfer mode is
selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other in
the frame. This differs from left-justified mode, where the left and right channel data will always be a half-frame
apart in each frame. In this case, as the offset is programmed from zero to some higher value, both the left and
right channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in
Figure 25 for the two cases.
26
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3106-Q1
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