參數(shù)資料
型號： 6PAIC3106IRGZRQ1
廠商： Texas Instruments
文件頁數(shù)： 51/103頁
文件大?。?/td> 0K
描述： IC AUDIO CODEC STEREO 48-QFN
標準包裝： 1
類型： 立體聲音頻
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標準 ADC / DAC (db)： 92 / 102（差分），92 / 95（單端）
動態(tài)范圍，標準 ADC / DAC (db)： 91 / 99（差分），91 / 92（單端）
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.1 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤
供應商設備封裝： 48-VQFN 裸露焊盤（7x7）
包裝： 標準包裝
產(chǎn)品目錄頁面： 1077 (CN2011-ZH PDF)
其它名稱： 296-25253-6
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
Table 12. Page 0 / Register 4: PLL Programming Register B
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D2
R/W
0000 01
PLL J Value
0000 00: Reserved, do not write this sequence
0000 01: J = 1
0000 10: J = 2
0000 11: J = 3
…
1111 10: J = 62
1111 11: J = 63
D1–D0
R/W
00
Reserved, write only zeros to these bits
Table 13. Page 0 / Register 5: PLL Programming Register C(1)
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
PLL D value – Eight most significant bits of a 14-bit unsigned integer valid values for D are from zero to
9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be written into these
registers that would result in a D value outside the valid range.
(1)
Note that whenever the D value is changed, register 5 should be written, immediately followed by register 6. Even if only the MSB or
LSB of the value changes, both registers should be written.
Table 14. Page 0 / Register 6: PLL Programming Register D
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D2
R/W
0000 0000
PLL D value – Six least significant bits of a 14-bit unsigned integer valid values for D are from zero to
9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be written into these
registers that would result in a D value outside the valid range.
D1–D0
R
00
Reserved, write only zeros to these bits.
Table 15. Page 0 / Register 7: Codec Datapath Setup Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
fS(ref) setting
This register setting controls timers related to the AGC time constants.
0: fS(ref) = 48 kHz
1: fS(ref) = 44.1 kHz
D6
R/W
0
ADC Dual rate control
0: ADC dual rate mode is disabled
1: ADC dual rate mode is enabled
Note: ADC Dual Rate Mode must match DAC Dual Rate Mode
D5
R/W
0
DAC Dual Rate Control
0: DAC dual rate mode is disabled
1: DAC dual rate mode is enabled
D4–D3
R/W
00
Left DAC Datapath Control
00: Left DAC datapath is off (muted)
01: Left DAC datapath plays left channel input data
10: Left DAC datapath plays right channel input data
11: Left DAC datapath plays mono mix of left and right channel input data
D2–D1
R/W
00
Right DAC Datapath Control
00: Right DAC datapath is off (muted)
01: Right DAC datapath plays right channel input data
10: Right DAC datapath plays left channel input data
11: Right DAC datapath plays mono mix of left and right channel input data
D0
R/W
0
Reserved. Only write zero to this register.
Copyright 2009–2012, Texas Instruments Incorporated
51
Product Folder Links: TLV320AIC3106-Q1
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