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參數(shù)資料
| 型號： | 6PAIC3106IRGZRQ1 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 89/103頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO CODEC STEREO 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 92 / 102（差分），92 / 95（單端） |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 91 / 99（差分），91 / 92（單端） |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 1.1 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-VQFN 裸露焊盤（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1077 (CN2011-ZH PDF) |
| 其它名稱： | 296-25253-6 |
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SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
Table 118. Page 0 / Register 109: DAC Quiescent Current Adjustment Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
DAC Current Adjustment
00: Default
01: 50% increase in DAC reference current
10: Reserved
11: 100% increase in DAC reference current
D5–D0
R/W
00 0000
Reserved. Write only zero to these register bits.
Table 119. Page 0 / Register 110–127: Reserved Registers
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R
0000 0000
Reserved. Do not write to these registers.
Page 1 / Register 0: Page Select Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D1
X
0000 000
Reserved, write only zeros to these register bits
D0
R/W
0
Page Select Bit
Writing zero to this bit sets Page-0 as the active page for following register accesses. Writing a one to
this bit sets Page-1 as the active page for following register accesses. It is recommended that the user
read this register bit back after each write, to ensure that the proper page is being accessed for future
register read/writes. This register has the same functionality on page-0 and page-1.
Page 1 / Register 1:
Left Channel Audio Effects Filter N0 Coefficient MSB Register(1)
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0110 1011
Left Channel Audio Effects Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-
complement integer, with possible values ranging from –32768 to 32767.
(1)
When programming any coefficient value in Page 1, the MSB register should always be written first, immediately followed by the LSB
register. Even if only the MSB or LSB of the coefficient changes, both registers should be written in this sequence.
Page 1 / Register 2:
Left Channel Audio Effects Filter N0 Coefficient LSB Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
1110 0011
Left Channel Audio Effects Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-
complement integer, with possible values ranging from –32768 to 32767.
Page 1 / Register 3:
Left Channel Audio Effects Filter N1 Coefficient MSB Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
1001 0110
Left Channel Audio Effects Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-
complement integer, with possible values ranging from –32768 to 32767.
Page 1 / Register 4: Left Channel Audio Effects Filter N1 Coefficient LSB Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0110 0110
Left Channel Audio Effects Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-
complement integer, with possible values ranging from –32768 to 32767.
86
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3106-Q1
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