參數(shù)資料
型號(hào)： 73S1217F-EB-LITE
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 86/93頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL 73S1217F CBL/DOC/CD
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
系列： *
UG_12xxF_016
73S12xxF Software User Guide
Rev. 1.50
87
Initialization
Get Delay Time
(in Secs)
Power-Up Ok
(Good ATR)?
Start Test by sending a
Block Transfer (0x6F)
with 0 Lenth data
EMV Power
Down
Single Shot
Select Single-Shot or
Loopback test?
Delay Time Wait
EMV Power Up
Yes
SingleShot?
Yes
No
Escape command is sent
with B1 = MCI(10) or
VISA I (20) or VISA II
(40) in EMVmode
Setup EMV Test
Mode
LoopBack
Figure 11: EMV PSE Test Flow Chart
4.5.1.2 MasterCard Loopback Test
Teridian used the CETECOM test lab in Germany and the FIME test lab in France (both listed on the
www.emvco.com website) for MasterCard Loopback verification. These labs used the MCI test suite for
their EMV Level I qualification test services.
Figure 12 and Figure 13 show the flow of the entire MCI test suite with the coding to be done on both the
host side (invokes the test) and the device side (manages all aspect of the smart card’s EMV test).
These test flows are specific to both the FIME and the Cetecom’s Level I Protocol test scripts. Source
code is also included in the release.
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