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IDT EJTAG System
EJTAG Processor Core Extensions
79RC32438 User Reference Manual
20 - 27
November 4, 2002
Notes
CountDM
25
Controls or indicates the Count register behavior in Debug
Mode. Implementations can have fixed behavior, in which case
this bit is read-only (R), or the implementation can allow this bit
to control the behavior, in which case this bit is read/write (R/
W).
The reset value of this bit indicates the behavior after reset,
and depends on the implementation.
R
1
Note:
This
value is
always 1.
IBusEP
24
Indicates if a Bus Error exception is pending from an instruction
fetch. Set when an instruction fetch bus error event occurs or a
1 is written to the bit by software. Cleared when a Bus Error
exception on an instruction fetch is taken by the processor. If
IBusEP is set when IEXI is cleared, a Bus Error exception on
an instruction fetch is taken by the processor, and IBusEP is
cleared.
In Debug Mode, a Bus Error exception applies to a Debug
Mode Bus Error exception.
R/W1
0
MCheckP
23
Indicates if a Machine Check exception is pending. Set when a
machine check event occurs or a 1 is written to the bit by soft-
ware. Cleared when a Machine Check exception is taken by
the processor. If MCheckP is set when IEXI is cleared, a
Machine Check exception is taken by the processor, and
MCheckP is cleared.
In Debug Mode, a Machine Check exception applies to a
Debug Mode Machine Check exception.
R/W
0
Note:
This
value is
always 0.
CacheEP
22
Indicates if a Cache Error is pending. Set when a cache error
event occurs or a 1 is written to the bit by software. Cleared
when a Cache Error exception is taken by the processor. If
CacheEP is set when IEXI is cleared, a Cache Error exception
is taken by the processor, and CacheEP is cleared.
In Debug Mode, a Cache Error exception applies to a Debug
Mode Cache Error exception.
R/W1
0
Note:
This
value is
always 0.
DBusEP
21
Indicates if a Data Access Bus Error exception is pending. Set
when a data access bus error event occurs or a 1 is written to
the bit by software. Cleared when a Bus Error exception on
data access is taken by the processor. If DBusEP is set when
IEXI is cleared, a Bus Error exception on data access is taken
by the processor, and DBusEP is cleared.
In Debug Mode, a Bus Error exception applies to a Debug
Mode Bus Error exception.
R/W1
0
IEXI
20
An Imprecise Error eXception Inhibit (IEXI) controls exceptions
taken due to imprecise error indications. Set when the proces-
sor takes a debug exception or an exception in Debug Mode
occurs. Cleared by execution of the DERET instruction. Other-
wise modifiable by Debug Mode software.
When IEXI is set, then the imprecise error exceptions from bus
errors on instruction fetches or data accesses, cache errors, or
machine checks are inhibited and deferred until the bit is
cleared.
R/W
0
Fields
Name Bits
Description
Read/
Write
Reset
State
Table 20.16 Debug Register Field Descriptions (Part 2 of 4)