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IDT EJTAG System
Hardware Breakpoints
79RC32438 User Reference Manual
20 - 50
November 4, 2002
Notes
The Data Breakpoint Control n (DBCn) register what constitutes data breakpoint n: triggerpoint, break-
point, ASID value inclusion, load/store access fulfillment, ignore byte access, byte lane mask. This register
is located at drseg offset 0x2118 + 0x100 * n. The “data bus” is described in section “Conditions for
Matching Data Breakpoints” on page 20-37. Figure 20.18 shows the format of the DBCn register and Table
20.39 describes the DBCn register fields.
Figure 20.18 DBCn Register Format
31
24
23
22
18 17
14 13 12 11
BAI[7:0]
No
SB
8
7
4
3
0
2
1
0
0
0
ASID
use
0
No
LB
0
BLM[7:0]
TE
BE
Fields
Description
Read/
Write
Reset
State
Compli-
ance
Name
Bit
ASIDuse
23
Use ASID value in compare for data break-
point n:
0:
Do not use ASID value in compare
1:
Use ASID value in compare
Debug software should only set the ASI-
Duse if a TLB in the implementation is
used by the application software.
This bit is read-only and reads as zero, if
not implemented.
R/W
Undefined
Required if
ASIDsup in
DBS reg. is 1,
otherwise not
implemented
BAI[7:0]
21:14
Byte access ignore. Controls ignore of
access to specific bytes. BAI[0] ignores
access to byte at bits [7:0] of the data bus,
BAI[1] ignores access to byte at bits [15:8],
etc.:
0:
Condition depends on access to cor-
responding byte
1:
Access for corresponding byte is
ignored.
Debug software must adjust for endianess
when programming this field.
BAI[7:4] are read-only (R) and read as
zeros for 32-bit processors.
R/W
Undefined
Required for
byte lanes in
implementa-
tion, other-
wise not
implemented.
NoSB
13
Controls whether condition for data break-
point is ever fulfilled on a store access:
0:
Condition can be fulfilled on store
access
1:
Condition is never fulfilled on store
access
R/W
Undefined
Required
NoLB
12
Controls whether condition for data break-
point is ever fulfilled on a load access:
0:
Condition can be fulfilled on load
access
1:
Condition is never fulfilled on load
access
R/W
Undefined
Required
Table 20.39 DBCn Register Field Description (Part 1 of 2)