IDT MIPS32 4Kc Processor Core
Exceptions
79RC32438 User Reference Manual
2 - 42
November 4, 2002
Notes
Debug exception vector
Debug Interrupt Exception
A debug interrupt exception is either caused by the EjtagBrk bit in the EJTAG Control register (controlled
through the TAP), or caused by the debug interrupt request signal to the CPU.
The debug interrupt exception is an asynchronous debug exception which is taken as soon as possible,
but with no specific relation to the executed instructions. The DEPC register is set to the instruction where
execution should continue after the debug handler is through. The DBD bit is set based on whether the
interrupted instruction was executing in the delay slot of a branch.
Debug Register Debug Status Bit Set
DINT
Additional State Saved
None
Entry Vector Used
Debug exception vector
Non-Maskable Interrupt (NMI) Exception
A non-maskable interrupt exception occurs when the SI_NMI signal is asserted to the processor.
SI_NMI is an edge sensitive signal - only one NMI exception will be taken each time it is asserted. An NMI
exception occurs only at instruction boundaries, so it does not cause any reset or other hardware initializa-
tion. The state of the cache, memory, and other processor states are consistent and all registers are
preserved, with the following exceptions:
The BEV, TS, SR, NMI, and ERL fields of the Status register are initialized to a specified state.
The ErrorEPC register is loaded with PC-4 if the state of the processor indicates that it was execut-
ing an instruction in the delay slot of a branch. Otherwise, the ErrorEPC register is loaded with PC.
PC is loaded with 0xBFC0_0000.
Cause Register ExcCode Value:
None
Additional State Saved:
None
Entry Vector Used:
Reset (0xBFC0_0000)
Operation:
StatusBEV << 1
StatusTS << 0
StatusSR << 0
StatusNMI << 1
StatusERL << 1
if InstructionInBranchDelaySlot then
ErrorEPC << PC - 4
else
ErrorEPC << PC
endif
PC << 0xBFC0_0000
Machine Check Exception
A machine check exception occurs when the processor detects an internal inconsistency. The following
condition causes a machine check exception: