Notes
79RC32438 User Reference Manual
9 - 1
November 4, 2002
Chapter 9
DMA Controller
Introduction
The DMA controller consists of 10 independent DMA channels, all of which operate in exactly the same
manner. All DMA channels support fly-by DMA operations between memory and a peripheral device.
1
A
single DMA channel may be multiplexed among two different devices using the device select (DS) field in a
DMA descriptor (refer to Table 9.2). The external DMA channels (i.e., DMA channels 0 and 1) use the
device select field to determine the direction of the DMA transfer (memory to external peripheral or external
peripheral to memory). The DS field is unused by the other DMA channels and must be set to zero.
Features
10 DMA channels
–
Two channels for PCI (PCI to Memory and Memory to PCI)
–
Four Ethernet channels — two for each Ethernet interface (transmit/receive)
–
Two DMA channels for memory to memory DMA operations
–
Two DMA channels for external DMA operations
Provides flexible descriptor based operation
Supports external peripheral DMA operations
Supports unaligned transfers (i.e., source or destination address may be on any byte boundary)
with arbitrary byte length
DMA Registers
1.
DMA operations are automatically supported across memory regions (for example, across DDR bank 0 and
DDR bank 1) as long as the physical addresses are contiguous and the memory regions have a size which is
greater than 64 KB.
Register Offset
1
Register Name
Register Function
Size
0x04_0000
DMA0C
DMA 0 control
32-bit
0x04_0004
DMA0S
DMA 0 status
32-bit
0x04_0008
DMA0SM
DMA 0 status mask
32-bit
0x04_000C
DMA0DPTR
DMA 0 descriptor pointer
32-bit
0x04_0010
DMA0NDPTR
DMA 0 next descriptor pointer
32-bit
0x04_0014
DMA1C
DMA 1 control
32-bit
0x04_0018
DMA1S
DMA 1 status
32-bit
0x04_001C
DMA1SM
DMA 1 status mask
32-bit
0x04_0020
DMA1DPTR
DMA 1 descriptor pointer
32-bit
0x04_0024
DMA1NDPTR
DMA 1 next descriptor pointer
32-bit
0x04_0028
DMA2C
DMA 2 control
32-bit
0x04_002C
DMA2S
DMA 2 status
32-bit
Table 9.1 DMA Register Map (Part 1 of 3)