- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378210 > 8051F330 (Electronic Theatre Controls, Inc.) Mixed Signal ISP Flash MCU Family PDF資料下載
參數(shù)資料
| 型號： | 8051F330 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Mixed Signal ISP Flash MCU Family |
| 中文描述： | 混合信號ISP的閃存微控制器系列 |
| 文件頁數(shù)： | 74/214頁 |
| 文件大?。?/td> | 2408K |
| 代理商： | 8051F330 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁當(dāng)前第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁
C8051F330/1/2/3/4/5
74
Rev. 1.4
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-program-
mable Flash can also be read and changed a single byte at a time by the application software using the
MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data stor-
age as well as updating program code under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in
Section “20. C2 Interface” on page 209
.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, macro assembler, debugger and pro-
grammer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast
and efficient in-system device programming and debugging. Third party macro assemblers and C compil-
ers are also available.
9.1.
Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51 instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51 counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
9.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 9.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
9.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory (Note: the C8051F330/1/2/3/4/5
does not support off-chip data or program memory). In the CIP-51, the MOVX instruction can be used to
access on-chip XRAM or on-chip program memory space implemented as re-programmable Flash mem-
ory. The Flash access feature provides a mechanism for the CIP-51 to update program code and use the
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 80546KF | 64-bit Intel Xeon Processor MP with up to 8MB L3 Cache |
| 8085AH | 8 BIT HMOS MICROPROCESSORS |
| 8085AH-1 | 8 BIT HMOS MICROPROCESSORS |
| 8085AH-2 | 8 BIT HMOS MICROPROCESSORS |
| 8087 | MATH COPROCESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8051F362-GM | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 8052 | 功能描述:連接線 24AWG 1C 404ft 1/2 POUND SPOOL RoHS:否 制造商:Belden Wire & Cable 絞合:19 x 32 電壓額定值:1 kV 長度:1000 ft 線規(guī) - 美國線規(guī)（AWG）:20 絕緣材料:Tetraflouroethylene (TFE) 最大溫度:+ 200 C 類型:High Temperature, High Voltage 外殼顏色:Blue (Light) 系列:83027 |
| 805200 | 制造商:BOSTIK 功能描述:EVO-STIK 528 ADHESIVE 500ML |
| 8052-0-0 | 制造商:Belden Inc 功能描述:SINGLE CONDUCTOR WIRE ROHS COMPLIANT:NO |
| 805-2000 | 制造商:Xantrex Technology Inc 功能描述:INVERTER/CHARGER, 2KW, 117V; No. of Outputs:1; Input Voltage Max:16VDC; Output Power:2kW; Output Voltage:117VAC; Output Current:17A; Length:145mm; Width:285mm; Height:450mm; Input Voltage:10V DC to 16V DC; Weight:24lb ;RoHS Compliant: NA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。