LPC Interface Bridge Registers (D31:F0)
9-66
Intel
82801BA ICH2 Datasheet
9.8.3.8
GPE0_EN—General Purpose Event 0 Enables Register
I/O Address:
PMBASE + 2Ah
(
ACPI GPE0_BLK + 2)
0000h
No
Bits 0–7 Resume,
Bits 8–15 RTC
Attribute:
Size:
Usage:
R/W
16-bit
ACPI
Default Value:
Lockable:
Power Well:
Note:
This register is symmetrical to the General Purpose Event 0 Status Register. All the bits in this
register should be cleared to 0 based on a Power Button Override. The resume well bits are all
cleared by RSMRST#. The RTC sell bits are cleared by RTCRST#.
Bit
Description
15:12
Reserved.
11
PME# Enable (PME_EN)
—R/W.
0 = Disable.
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be
a wake event from the S1–S4 state or from S5 (if entered via SLP_EN, but not power button
override).
9
Reserved
8
RI_EN
—R/W.
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
7
Reserved
6
TCO SCI Enable (TCOSCI_EN)
—R/W.
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
5
AC97 Enable (AC97_EN)
—R/W.
0 = Disable.
1 = Enables the setting of the AC97_STS to generate a wake event.
4
USB Controller 2 Enable (USB2_EN)
—R/W.
0 = Disable.
1 = Enables the setting of the USB2_STS to generate a wake event.
3
USB Controller 1 Enable (USB1_EN)
—R/W.
0 = Disable.
1 = Enables the setting of the USB1_STS to generate a wake event.
2
Thermal Pin Polarity (THRM#_POL)
—R/W. This bit controls the polarity of the THRM# pin
needed to set the THRM_STS bit.
0 = Low value on the THRM# signal will set the THRM_STS bit.
1 = HIGH value on the THRM# signal will set the THRM_STS bit.
1
Reserved.
0
Thermal Signal Reporting Enable (THRM_EN)
—R/W.
0 = Disable.
1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the
THRM_STS bit and generate a power management event (SCI or SMI).
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