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82801BA ICH2
Datasheet
Contents
1
Introduction................................................................................................................1-1
1.1
About this Document ....................................................................................1-1
1.2
Overview.......................................................................................................1-3
2
Signal Description......................................................................................................2-1
2.1
Hub Interface to Host Controller...................................................................2-1
2.2
Link to LAN Connect.....................................................................................2-1
2.3
EEPROM Interface .......................................................................................2-2
2.4
Firmware Hub Interface ................................................................................2-2
2.5
PCI Interface.................................................................................................2-2
2.6
IDE Interface.................................................................................................2-4
2.7
LPC Interface................................................................................................2-6
2.8
Interrupt Interface .........................................................................................2-6
2.9
USB Interface ...............................................................................................2-7
2.10
Power Management Interface.......................................................................2-7
2.11
Processor Interface.......................................................................................2-8
2.12
SMBus Interface ...........................................................................................2-9
2.13
System Management Interface.....................................................................2-9
2.14
Real Time Clock Interface ..........................................................................2-10
2.15
Other Clocks...............................................................................................2-10
2.16
Miscellaneous Signals................................................................................2-10
2.17
AC’97 Link ..................................................................................................2-11
2.18
General Purpose I/O...................................................................................2-11
2.19
Power and Ground......................................................................................2-12
2.20
Pin Straps...................................................................................................2-12
2.20.1 Functional Straps...........................................................................2-12
2.20.2 Test Signals...................................................................................2-13
2.20.2.1 Test Mode Selection.......................................................2-13
2.20.2.2 Test Straps.....................................................................2-13
2.20.3 External RTC Circuitry...................................................................2-14
2.20.4 V5REF / Vcc3_3 Sequencing Requirements.................................2-14
3
ICH2 Power Planes and Pin States...........................................................................3-1
3.1
Power Planes................................................................................................3-1
3.2
Integrated Pull-Ups and Pull-Downs.............................................................3-1
3.3
IDE Integrated Series Termination Resistors ...............................................3-2
3.4
Output and I/O Signals Planes and States...................................................3-2
3.5
Power Planes for Input Signals.....................................................................3-5
4
ICH2 and System Clock Domains .............................................................................4-1
5
Functional Description...............................................................................................5-1
5.1
Hub Interface to PCI Bridge (D30:F0)...........................................................5-1
5.1.1
PCI Bus Interface.............................................................................5-1
5.1.2
PCI-to-PCI Bridge Model .................................................................5-2
5.1.3
IDSEL to Device Number Mapping..................................................5-2
5.1.4
SERR# Functionality........................................................................5-2
5.1.5
Parity Error Detection ......................................................................5-4
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