- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376472 > 82C931 (Electronic Theatre Controls, Inc.) Plug and Play Integrated Audio Controller PDF資料下載
參數(shù)資料
| 型號： | 82C931 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Plug and Play Integrated Audio Controller |
| 中文描述： | 即插即用集成音頻控制器 |
| 文件頁數(shù)： | 28/64頁 |
| 文件大?。?/td> | 634K |
| 代理商： | 82C931 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
82C931
Page 20
912-3000-035
Revision: 2.1
OPTi
4.2
16-Bit Codec/Mixer
4.2.1
Features of the built-in 16-bit stereo sigma-delta codec
include:
Codec
Sigma-delta stereo ADC with 128X over-sampling
Sigma-delta stereo DAC with 128X over-sampling
On-chip 8X Interpolation Filter
On-chip analog post filter
Single-ended input and output
Sampling rate of 5KHz to 48KHz
The codec serial interface provides a means to read and
write 16-bit stereo data from the ADC or to the DAC respec-
tively. The interface (as shown in Figure 4-1) consists of the
following lines:
DAC[15:0] - to write to the DAC 16-bit input
ADC[15:0] - to read the ADC 16-bit output
L/R - to select between the left and right channels for both
the ADC and DAC data.
MCLK - This internal master clock signal is synthesized by
the frequency synthesizer from the crystal reference of
14.318MHz. One of 236 frequencies may be selected
through the 8-bit FSEL line. MCLK is not active when the
frequency synthesizer is powered down. The frequency of
MCLK is 256 times the sampling frequency.
The DAC left/right 16-bit input data are multiplexed onto
DAC[15:0] and fed into the codec. The L/R signal qualifies
the data. The period of L/R is equal to that of the codec sam-
pling frequency. One set of left/right 16-bit input data to the
DAC is sent every L/R cycle. When L/R is low, the data on
DAC[15:0] is meant for the left channel; when L/R is high, the
data is meant for the right channel. This means that the DAC
treats data packets L1 and R1 as belonging to the same sam-
pling instance; while L2 and R2 are data for the next sam-
pling instance.
The ADC left/right 16-bit output data are similarly multiplexed
onto the ADC[15:0] bus.
Figure 4-1
Functional Block Diagram
AVCC
AGND
CINR
CINL
DACL
DACR
VREF
MCLK
Stereo 16-Bit Sigma-Delta ADC
Analog
Sigma-Delta
Modulator
128:1
1
128fs
16
Analog
Low-Pass
Filter
fs
16
S
Stereo 16-Bit Sigma-Delta DAC
Digital
Sigma-Delta
Modulator
8fs
8X
Voltage Reference
Clock Generation
Power Supply
VCC VCC
PD
Decimation
Filter
Analog
Sigma-Delta
Modulator
128:1
Decimation
Filter
1
128fs
16
fs
Interpolator
Analog
Low-Pass
Digital
Sigma-Delta
Modulator
8X
Interpolator
16
8fs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S19 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S101BYA | 2.6GHz Relay, 1 Form C, 0.5A 30VDC Relay, 50ohms, SMD |
| 82S100BXA | 1 MSPS, 12-Bit A/D Converter in MSOP-8 or SOIC-8; Package: MSOP; No of Pins: 8; Temperature Range: Industrial |
| 82S101 | Field Programmable Logic Array |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C931(100PQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Soundcard Circuits |
| 82C931(100TQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Soundcard Circuits |
| 82C941 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| 82-CBSA-1.75X6.0X0.8 | 功能描述:82-CBSA-1.75X6.0X0.8--82S04--CIR 制造商:leader tech inc. 系列:* 零件狀態(tài):在售 類型:屏蔽，分體式 高度 - 總:0.800"（20.32mm） 長度 - 總:6.000"（152.40mm） 寬度 - 總:1.750"（44.45mm） 通風(fēng):通風(fēng)孔，按樣式排列 安裝類型:通孔 標(biāo)準(zhǔn)包裝:50 |
| 82-CBSA-3.75X4.5X0.8 | 功能描述:82-CBSA-3.75X4.5X0.8--82S12--CIR 制造商:leader tech inc. 系列:* 零件狀態(tài):在售 類型:屏蔽，分體式 高度 - 總:0.800"（20.32mm） 長度 - 總:4.500"（114.30mm） 寬度 - 總:3.750"（95.25mm） 通風(fēng):通風(fēng)孔，按樣式排列 安裝類型:通孔 標(biāo)準(zhǔn)包裝:50 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。