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參數(shù)資料
| 型號： | 82C931 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Plug and Play Integrated Audio Controller |
| 中文描述： | 即插即用集成音頻控制器 |
| 文件頁數(shù)： | 47/64頁 |
| 文件大?。?/td> | 634K |
| 代理商： | 82C931 |
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82C931
912-3000-035
Revision: 2.1
Page 39
OPTi
WSBase+06h
Codec Status Register (R/W, exists in Codec only)
Default = 44h
PIO capture
data is ready for
upper or lower
byte (RO):
0 = Lower
1 = Upper (or
any 8-bit mode)
data is waiting
for right or left
channel ADC
(RO):
0 = Right
1 = Left (or
mono)
PIO Capture
Data Register
contains data
ready for read-
ing by host
(RO):
(1)
0 = Stale ADC
data (do not re-
read)
1 = Fresh ADC
data (ready for
next host data
read)
Sample
over/underrun
(RO):
Indicates that
the most recent
sample was not
serviced in time;
therefore either
an overrun for
ADC capture or
underrun for
DAC playback
has occurred.
(2)
PIO playback
data is needed
for upper or
lower byte
(RO):
0 = Lower
1 = Upper (or
any 8-bit mode)
PIO playback
data is needed
for right or left
channel DAC
(RO):
0 = Right
1 = Left (or
mono)
PIO Playback
Data Register
ready for more
data (RO):
(1)
0 = Valid DAC
data (do not
overwrite)
1 = Stale DAC
data (ready for
next host data
write value)
Interrupt:
0 = Disable
1 = Enable
(1) These bits (5 and 1) should only be programmed when direct programmed I/O data transfers are desired.
(2) If both capture and playback are enabled, the source which set bit 4 ca be determined by reading COR and PUR. Bit 4 changes on a sam-
ple-by-sample basis.
Note:
Bits 5, 1, and 0 can change asynchronously to host accesses. The host may access this register while the bits are transitioning. The
host read may return a zero value just as these bits are changing (e.g., a value of 1 would not be read until the next host access).
This register’s initial state after reset is "1100 1100".
WSBase+07h
Codec Direct Data Register - Capture Mode (RO, exists in Codec only)
Default = 00h
The Codec Direct Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register
(PD7:0). Reads will receive data from the PIO Capture Data Register (CD7:0).
During initialization, the PIO Playback Data Register cannot be written and the Capture Data Register is always read "1000 0000" (80h).
PIO Capture Data Register:
This is the control register where capture data is read during programmed I/O data transfers.
The reading of this register will increment the state machine so that the following read will be from the next appropriate byte in the sample. The
exact byte which is next to be read can be determined by reading the Status Register. Once all relevant bytes have been read, the state
machine will stay pointed to the last byte of the sample until a new sample is received from the ADCs. Once this has occurred, the state
machine and status register will point to the first byte of the sample. Until a new sample is received, reads from this register will return the most
significant byte of the sample.
WSBase+07h
Codec Direct Data Register - Playback Mode (WO, exists in Codec only)
Default = 00h
The Codec Direct Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register
(PD7:0). Reads will receive data from the PIO Capture Data Register (CD7:0).
During initialization, the PIO Playback Data Register cannot be written and the Capture Data Register is always read "1000 0000" (80h).
PIO Playback Data Register:
This is the control register where playback data is written during programmed I/O data transfers.
Writing data to this register will increment the playback byte tracking state machine so that the following write will be to the correct byte of the
sample. Once all bytes of a sample have been written, subsequent byte writes to this port are ignored. The state machine is reset when the
current sample is sent to the DACs.
Table 5-9
WSBase Register for Codec/Mixer Applications (cont.)
7
6
5
4
3
2
1
0
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