參數(shù)資料
型號(hào)： 82C931
廠商： Electronic Theatre Controls, Inc.
英文描述： Plug and Play Integrated Audio Controller
中文描述： 即插即用集成音頻控制器
文件頁(yè)數(shù)： 44/64頁(yè)
文件大?。?/td> 634K
代理商： 82C931
82C931
Page 36
912-3000-035
Revision: 2.1
OPTi
5.3
SBBase is mainly used to access the Digital Audio Processor
(DAP) registers, however, as shown in Table 5-7 other types
of registers are also accessible through SBBase. The index-
ing scheme is the same as when accessing MCBase regis-
SBBase Register
ters (CPU Direct I/O R/W). Note that in Table 5-7, which gives
the SBBase register bit formats, some registers may also be
accessed through ALBase. However, use only one Base reg-
ister for accessing.
Table 5-7
SBBase Registers for FM and DAP Applications
7
6
5
4
3
2
1
0
SBBase+00h (or ALBase+00h)
Left FM Status Register (RO)
SBBase+00h (or ALBase+00h)
Left FM Address Port Register (WO)
SBBase+01h (or ALBase+01h)
Left FM Data Port Register (WO)
SBBase+02h (or ALBase+02h)
Right FM Address Port Register (WO)
SBBase+03h (or ALBase+03h)
Right FM Data Port Register (WO)
SBBase+04h
Mixer Address Port Register (WO)
SBBase+05h
Mixer Data Port Register (WO)
SBBase+06h
DAP Reset Register
Don't care
DAP software
reset at end of
the I/O write
command:
0 = Disable
1 = Enable
(1)
(1) When bit 0 is enabled, it sets a software reset flag. This software reset is terminated by performing another write at this location with bit 0
= 0. A system reset will reset the software reset flag, thus terminating the software reset
SBBase+08h
FM Status Port Register (RO)
SBBase+08h
FM Address Port Register (WO)
SBBase+09h
FM Data Port Register (WO)
SBBase+0Ah
DAP Read Data Register (RO)
SBBase+0Ch
DAP Data/Command Register (WO)
SBBase+0Ch
DAP Write Buffer Status Register (RO)
DAP Input
buffer full:
(1)
0 = Empty
1 = Full
(1)This flag is set when the host CPU writes data in the input data bus buffer and cleared when the data is read by the internal DAP.
SBBase+A[6:0]
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