參數(shù)資料
型號(hào)： 82C931
廠商： Electronic Theatre Controls, Inc.
英文描述： Plug and Play Integrated Audio Controller
中文描述： 即插即用集成音頻控制器
文件頁(yè)數(shù)： 43/64頁(yè)
文件大?。?/td> 634K
代理商： 82C931
82C931
912-3000-035
Revision: 2.1
Page 35
OPTi
MCIR23
Serial Audio Clock/Output Control Register
Default = 00h
ASDOOE
ADO direction
control
0 = Input
1 = Output
SCLKOE
SCLK direction
control
0 = Input
1 = Output
FSYNCOE
FSYNC direc-
tion control
0 = Input
1 = Output
MCLKEN
External MCLK
enable (fed
through ASDO)
0 = Disabled
1 = Enabled
MCLKSEL[1:0]
Master clock divider selection
00 = asdo_clk/8
01 = asdo_clk/4
10 = asdo_clk/2
11 = asdo_clk/1
CLKSEL[1:0]
Selects shift clock for serial audio
data output (sclk_out)
00 = mclk/8
01 = mclk/4
10 = mclk/2
11 = mclk/1
MCIR24
Game Port Counter Setup and Status Register
Default = 00h
JRDY/Game
Port IRQ
Readback of ’1’
indicates the
game port
counters are
stopped and the
interrups is gen-
erated. The IRQ
is cleared by
writing a ’1’ to
this location.
SOUNDIRQ
Shows the sta-
tus of the audio
IRQ, a ’1’ indi-
cates there is a
soundIRQ
GPIRQEN
IRQ generation
when the game
port counter is
finish counting
0 = Disabled
1 = Enabled
GPWPEN
Auto game port
trigger (20x
write)
0 = Disabled
1 = Enabled
ACTBY
By axis counter
enable
0 = Disabled
1 = Enabled
ACTBX
Bx axis counter
enable
0 = Disabled
1 = Enabled
ACTAY
Ay axis counter
enable
0 = Disabled
1 = Enabled
ACTAX
Ax axis counter
enable
0 = Disabled
1 = Enabled
MCIR25
Game Port Counter Values Register
Default = xxh
GPCOUNT[7:0]
Hardware counter values in H-byte L-byte fashion (16-bit). The sequence will be:
Joystick A-X axis
Joystick A-Y axis
Joystick B-X axis
Joystick B-Y axix
The count value will be changed automatically upon each read of this register. If that particular joystick axis is maksed (disabled), the count
will skip accordingly.
MCIR26
FDAC Data Control Register
Default = 00h
JPTSTEN
Game port
counter test
mode, counter
toggled by
14.318MHz
(default=1MHz)
0 = Disabled
1 = Enabled
Reserved
VCPIN
Special volume
control pins
move the pins
to
up/down=GD5/
4 (normal:
up/down =
GD7/6
0 = Disabled
1 = Enabled
ASWTST
FDAC data
auto-switching
timer test mode,
TxD timer tog-
gled by
14.318MHz
(default =
31KHz)
0 = Disabled
1 = Enabled
FDACMUL
Multiply FDAC
data by 2
0 = Disabled
1 = Enabled
FMMUL
Multiply FM
data by 2
0 = Disabled
1 = Enabled
FMDIV
Divide FM data
by 2
0 = Disabled
1 = Enabled
AUTOSW
Auto-detect of
TxD activity to
switch the
FDAC data
between FM
and serial
audio (which
comes from
TxD
0 = Disabled
1 = Enabled
Table 5-6
MC Indirect Registers (cont.)
7
6
5
4
3
2
1
0
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