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參數(shù)資料
| 型號： | 97022-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 300 MHz, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 566K |
| 代理商： | 97022-99 |
Product Specification
PE97022
Page 2 of 15
2007-2010 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0235-05
│ UltraCMOS RFIC Solutions
Table 1. Pin Descriptions
Figure 2. Pin Configurations (Top View)
44-lead CQFJ
Figure 3. Package Type
11
12
13
14
15
16
17
10
9
8
7
6
5
4
3
2
1 44 43 42 41 40
35
34
33
32
31
30
29
36
37
38
39
18 19 20 21 22 23 24 25 26 27 28
D
0, M0
D
1, M1
D2, M2
D
3, M3
V
DD
V
DD
S_WR, D
4, M4
Sdata, D
5, M5
Sclk, D
6, M6
FSELS, D7, Pre_en
GND
fp
V
DD_fp
D
out
V
DD
C
ext
V
DD
PD_D
PD_U
V
DD_fc
f
c
F
in
F
in
H
op
_W
R
A
_W
R
M
1_
W
R
V
D
B
m
od
e
S
m
od
e,
A
3
M
2_
W
R
,
A
2
E
_W
R
,
A
1
F
S
E
LP
,A
0
G
N
D
R
3
R
2
R
1
R
0
V
D
E
nh
LD
fr
G
N
D
G
N
D
Pin No.
Pin Name
Interface Mode
Type
Description
1
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
2
R0
Direct
Input
R Counter bit0 (LSB).
3
R1
Direct
Input
R Counter bit1.
4
R2
Direct
Input
R Counter bit2.
5
R3
Direct
Input
R Counter bit3.
6
GND
ALL
(Note 1)
Ground.
7
D0
Parallel
Input
Parallel data bus bit0 (LSB).
M0
Direct
Input
M Counter bit0 (LSB).
8
D1
Parallel
Input
Parallel data bus bit1.
M1
Direct
Input
M Counter bit1.
9
D2
Parallel
Input
Parallel data bus bit2.
M2
Direct
Input
M Counter bit2.
10
D3
Parallel
Input
Parallel data bus bit3.
M3
Direct
Input
M Counter bit3.
11
VDD
ALL
(Note 1)
Same as pin 1.
12
VDD
ALL
(Note 1)
Same as pin 1.
13
S_WR
Serial
Input
Serial load enable input. While S_WR is “l(fā)ow”, Sdata can be serially clocked.
Primary register data is transferred to the secondary register on S_WR or Hop_WR
rising edge.
D4
Parallel
Input
Parallel data bus bit4
M4
Direct
Input
M Counter bit4
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