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參數(shù)資料
| 型號(hào)： | 97022-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 300 MHz, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 566K |
| 代理商： | 97022-99 |
Product Specification
PE97022
Page 3 of 15
Document No. 70-0235-05
│ www.psemi.com
2007-2010 Peregrine Semiconductor Corp. All rights reserved.
Table 1. Pin Descriptions (continued)
Pin No.
Pin Name
Interface Mode
Type
Description
14
Sdata
Serial
Input
Binary serial data input. Input data entered MSB first.
D5
Parallel
Input
Parallel data bus bit5.
M5
Direct
Input
M Counter bit5.
15
Sclk
Serial
Input
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“l(fā)ow”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
D6
Parallel
Input
Parallel data bus bit6.
M6
Direct
Input
M Counter bit6.
16
FSELS
Serial
Input
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
D7
Parallel
Input
Parallel data bus bit7 (MSB).
Pre_en
Direct
Input
Prescaler enable, active “l(fā)ow”. When “high”, Fin bypasses the prescaler.
17
GND
ALL
Ground.
18
FSELP
Parallel
Input
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
A0
Direct
Input
A Counter bit0 (LSB).
19
E_WR
Serial
Input
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Parallel
Input
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
A1
Direct
Input
A Counter bit1.
20
M2_WR
Parallel
Input
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
A2
Direct
Input
A Counter bit2.
21
Smode
Serial, Parallel
Input
Selects serial bus interface mode (Bmode
=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
A3
Direct
Input
A Counter bit3 (MSB).
22
Bmode
ALL
Input
Selects direct interface mode (Bmode
=1).
23
VDD
ALL
(Note 1)
Same as pin 1.
24
M1_WR
Parallel
Input
M1 write. D[7:0] are latched into the primary register (Pre_en
, M[6:0]) on the rising
edge of M1_WR.
25
A_WR
Parallel
Input
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge
of A_WR.
26
Hop_WR
Serial, Parallel
Input
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
27
Fin
ALL
Input
Prescaler input from the VCO. 3.5 GHz max frequency.
28
Fin
ALL
Input
Prescaler complementary input. A bypass capacitor in series with a 51
resistor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
29
GND
ALL
Ground.
30
fp
ALL
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
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