參數(shù)資料
型號： 9S12XDP512DGV2
英文描述： Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
中文描述： 設(shè)備用戶指南掩模組L15Y - （二硅-增強(qiáng)的功能集）
文件頁數(shù)： 121/152頁
文件大小： 1231K
代理商： 9S12XDP512DGV2
121
A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The
Table A-10
and
Table A-11
show conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V
SSA
≤
V
RL
≤
V
IN
≤
V
RH
≤
V
DDA
.
This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-10 ATD Operating Characteristics 5V
Conditions are shown in
Table A-4
unless otherwise noted, Supply Voltage 4.5V < VDDA < 5.5V
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
D
Reference Potential
Low
High
V
RL
V
RH
V
SSA
V
DDA
/2
4.50
V
DDA
/2
V
DDA
5.5
V
V
2
C Differential Reference Voltage
1
NOTES
:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
V
RH
-V
RL
f
ATDCLK
5.00
V
3
D ATD Clock Frequency
0.5
TBD
MHz
4
D
ATD 10-Bit Conversion Period
Clock Cycles
2
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
N
CONV10
T
CONV10
14
TBD
28
14
Cycles
μ
s
5
D
ATD 8-Bit Conversion Period
Clock Cycles
2
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
N
CONV8
T
CONV8
12
TBD
26
13
Cycles
μ
s
6
D Recovery Time (V
DDA
=5.0 Volts)
t
REC
I
REF
I
REF
20
μ
s
7
P
Reference Supply current 2 ATD blocks on
0.750
mA
8
P
Reference Supply current 1 ATD block on
0.375
mA
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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