參數資料
型號： 9S12XDP512DGV2
英文描述： Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
中文描述： 設備用戶指南掩模組L15Y - （二硅-增強的功能集）
文件頁數： 134/152頁
文件大小： 1231K
代理商： 9S12XDP512DGV2
MC9S12XDP512 Device User Guide — V01.12
134
A.5.1.5 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t
wrs
the CPU starts
fetching the interrupt vector.
A.5.2 Oscillator
The device features an internal low-power loop controlled Pierce oscillator and a full swing Pierce
oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset. Before asserting
theoscillatortotheinternalsystemclocksthequalityoftheoscillationischeckedforeachstartfromeither
power-on, STOP or oscillator fail. t
CQOUT
specifies the maximum time before switching to the internal
self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also
determines the minimum oscillator start-up time t
UPOSC
. The device also features a clock monitor. A
Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert
Frequency f
CMFA.
Table A-18 Oscillator Characteristics
Conditions are shown in
Table A-1
unless otherwise noted
Num
C
Rating
Symbol
Min
Typ
Max
Unit
1a
C Crystal oscillator range (loop controlled Pierce)
f
OSC
4.0
16
MHz
1b
C Crystal oscillator range (full swing Pierce)
1,2
NOTES
:
1. Depending on the crystal a damping series resistor might be necessary
2. XCLKS =0 during reset
3. f
osc
= 4MHz, C = 22pF.
4. Maximum value is for extreme cases using high Q, low frequency crystals
f
OSC
0.5
40
MHz
2
P Startup Current
i
OSC
100
μ
A
3
C Oscillator start-up time (loop controlled Pierce)
t
UPOSC
TBD
3
50
4
ms
4
D Clock Quality check time-out
t
CQOUT
0.45
2.5
s
5
P Clock Monitor Failure Assert Frequency
f
CMFA
50
100
200
ΚΗ
z
6
P External square wave input frequency
f
EXT
0.5
TBD
MHz
7
D External square wave pulse width low
t
EXTL
TBD
ns
8
D External square wave pulse width high
t
EXTH
TBD
ns
9
D External square wave rise time
t
EXTR
TBD
ns
10
D External square wave fall time
t
EXTF
TBD
ns
11
D Input Capacitance (EXTAL, XTAL inputs)
C
IN
TBD
pF
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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