參數(shù)資料
型號： 9S12XDP512DGV2
英文描述： Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
中文描述： 設(shè)備用戶指南掩模組L15Y - （二硅-增強(qiáng)的功能集）
文件頁數(shù)： 135/152頁
文件大?。?/td> 1231K
代理商： 9S12XDP512DGV2
135
A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL′s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Figure A-2 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K
1
, f
1
and i
ch
from
Table A-19
.
The grey boxes show the calculation for f
VCO
= 80MHz and f
ref
= 4MHz. E.g., these frequencies are used
for f
OSC
= 4MHz and a 40MHz bus clock.
The VCO gain at the desired VCO frequency is approximated by:
The phase detector relationship is given by:
i
ch
is the current in tracking mode.
f
osc
1
refdv+1
f
ref
Phase
Detector
VCO
K
V
1
synr+1
f
vco
Loop Divider
K
Φ
1
2
f
cmp
C
s
R
C
p
VDDPLL
XFC Pin
K
V
K
1
e
f
K
1
1V
vco
-----------f
)
=
195MHz V
–
e
126
–
80
–
195
----------------------
=
= -154.0MHz/V
K
Φ
i
ch
–
K
V
3.5
μ
A
–
154MHz
–
V
(
)
539.1Hz
=
=
=
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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