參數(shù)資料
型號： 9S12XDP512DGV2
英文描述： Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
中文描述： 設(shè)備用戶指南掩模組L15Y - （二硅-增強(qiáng)的功能集）
文件頁數(shù)： 19/152頁
文件大?。?/td> 1231K
代理商： 9S12XDP512DGV2
19
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Loop-back for self test operation
Enhanced Capture Timer
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16-bit main counter with 7-bit prescaler
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8 programmable input capture or output compare channels
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Four 8-bit or two 16-bit pulse accumulators
8 PWM channels
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Programmable period and duty cycle
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8-bit 8-channel or 16-bit 4-channel
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Separate control for each pulse width and duty cycle
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Center-aligned or left-aligned outputs
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Programmable clock select logic with a wide range of frequencies
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Fast emergency shutdown input
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Usable as interrupt inputs
Serial interfaces
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Six asynchronous Serial Communication Interfaces (SCI) with additional LIN support and
selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
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Three Synchronous Serial Peripheral Interfaces (SPI)
Two Inter-IC Bus modules (IIC)
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Compatible with I2C Bus standard
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Multi-master operation
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Software programmable for one of 256 different serial clock frequencies
On chip Voltage Regulator
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Two parallel, linear voltage regulators with bandgap reference
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Low Voltage detect (LVD) with Low Voltage Interrupt (LVI)
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Power On Reset (POR) circuit
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3.3V - 5.5V operation
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Low Voltage Reset (LVR)
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Ultra Low Power Wake-up Timer
144 Pin LQFP, 112-Pin LQFP package and 80-Pin QFP package
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I/O lines with 5V input and drive capability
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Input threshold on external bus interface inputs switchable for 3.3V or 5V operation
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5V A/D converter inputs
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Operation at 80MHz equivalent to 40MHz Bus Speed
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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