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| 型號(hào)： | 9S12XDP512DGV2 |
| 英文描述： | Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set) |
| 中文描述： | 設(shè)備用戶指南掩模組L15Y - （二硅-增強(qiáng)的功能集） |
| 文件頁(yè)數(shù)： | 17/152頁(yè) |
| 文件大?。?/td> | 1231K |
| 代理商： | 9S12XDP512DGV2 |
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17
Section 1 Introduction
1.1 Overview
The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efficiency
advantages currently enjoyed by users of Motorola's existing 16-Bit MC9S12 MCU family.
Based around an enhanced S12 core, the MC9S12XD-Family will deliver 2 to 5 times the performance of
a 25MHz S12 whilst retaining a high degree of pin and code compatibility with the S12.
The MC9S12XD-Family introduces the performance boosting XGATE module. Using enhanced DMA
functionality, this parallel processing module offloads the CPU by providing high speed data processing
and transfer between peripheral modules, RAM and I/O ports. Providing up to 80MIPS of performance
additional to the CPU, the XGATE can access all peripherals and the RAM block.
The MC9S12XDP512 is composed of standard on-chip peripherals including 512Kbytes of Flash
EEPROM,20KbytesofRAM,4KbytesofEEPROM,sixasynchronousserialcommunicationsinterfaces
(SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel,
10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converters, an 8-channel
pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12), two
Inter-IC Bus blocks and a Periodic Interrupt Timer. The MC9S12XDP512 has full 16-bit data paths
throughout. The non-multiplexed expanded bus interface available on the 144-Pin versions allows an easy
interface to external memories.
The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit
operational requirements. System power consumption can be further improved with the new “fast exit
from STOP mode” feature.
In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt
capability allowing Wake-Up from STOP or WAIT mode.
TheMC9S12XDP512willbeavailablein144-PinLQFPwithexternalbusinterfaceandin112-PinLQFP
or 80-Pin QFP package without external bus interface.
1.2 Features
HCS12X Core
–
16-bit HCS12X CPU
i. Upward compatible with MC9S12 instruction set
ii. Interrupt stacking and programmer’s model identical to MC9S12
iii.Instruction queue
iv.Enhanced indexed addressing
v. Enhanced instruction set
–
EBI (External Bus Interface)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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