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參數(shù)資料
| 型號： | A0800AMS3C |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 800 MHz, MICROPROCESSOR, CPGA462 |
| 封裝： | STAGGERED, CERAMIC, PGA-453 |
| 文件頁數(shù)： | 20/90頁 |
| 文件大?。?/td> | 1492K |
| 代理商： | A0800AMS3C |
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Chapter 4
Power Management
13
23792H—March 2001
AMD Athlon Processor Model 4 Data Sheet
Preliminary Information
Note: In response to Halt special cycles, the Northbridge passes the
Halt
special
cycle
to
the
PCI
bus
or
Southbridge
immediately.
The processor can receive an interrupt after it sends a Halt
special cycle, or STPCLK# deassertion after it sends a Stop
Grant s pecial cy cle to the Nor thbridge but befo re the
disconnect actually occurs. In this case, the processor sends the
Connect spe cia l cycle to the Nor thbridge , rather than
continuing with the disconnect sequence. In response to the
Connect special cycle, the Northbridge cancels the disconnect
request.
The system is required to assert the CONNECT signal before
returning the C-bit for the connect special cycle (assuming
CONNECT has been deasserted). For more information, see the
AMD Athlon System Bus Specification, order# 21902 for the
definition of the C-bit and the Connect special cycle.
Figure 4 shows the sequence of events from a Northbridge
perspective, which leads to disconnecting the processor from
the AMD Athlon system bus and placing the processor in the
Stop Grant state.
Figure 4. Example System Bus Disconnect Sequence
The following sequence of events describes how the processor is
placed in the Stop Grant state when bus disconnect is enabled
within the Northbridge:
1. The Southbridge asserts STPCLK# to place the processor in
the Stop Grant state.
2. When the processor recognizes STPCLK# asserted, the
processor enters the Stop Grant State, then issues a Stop
Grant special cycle on the AMD Athlon system bus.
Stop Grant
STPCLK#
CONNECT
PROCRDY
CLKFWDRST
PCI Bus
System Bus
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