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參數(shù)資料
| 型號： | A0800AMS3C |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 800 MHz, MICROPROCESSOR, CPGA462 |
| 封裝： | STAGGERED, CERAMIC, PGA-453 |
| 文件頁數(shù)： | 42/90頁 |
| 文件大?。?/td> | 1492K |
| 代理商： | A0800AMS3C |
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Chapter 7
Electrical Data
33
23792H—March 2001
AMD Athlon Processor Model 4 Data Sheet
Preliminary Information
TRISE
Signal Rise Time
1.0
3.0
V/ns
6
TFALL
Signal Fall Time
1.0
3.0
V/ns
6
CPIN
Pin Capacitance
4
12
pF
Table 13. General AC and DC Characteristics (continued)
Symbol
Parameter Description
Condition
Min
Max
Units
Notes
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE Min and VCC_CORE Max.
3. IOL and IOH are measured at VOL max and VOH min, respectively.
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to guarantee capture.
8. This value assumes RSTCLK frequency is 10ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, LowPower mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
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