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參數(shù)資料
| 型號： | A0800AMS3C |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 800 MHz, MICROPROCESSOR, CPGA462 |
| 封裝： | STAGGERED, CERAMIC, PGA-453 |
| 文件頁數(shù)： | 24/90頁 |
| 文件大?。?/td> | 1492K |
| 代理商： | A0800AMS3C |
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16
Power Management
Chapter 4
AMD Athlon Processor Model 4 Data Sheet
23792H—March 2001
Preliminary Information
Figure 7. Processor Connect State Diagram
Condition
1
CONNECT is deasserted by the Northbridge (for a
previously sent Halt or Stop Grant special cycle).
2
Processor receives a wake-up event and must cancel
the disconnect request.
3 Deassert PROCRDY and slow down internal clocks.
4
Processor wake-up event or CONNECT asserted by
Northbridge.
5 CLKFWDRST is deasserted by the Northbridge.
6
Forward clocks start 3 SYSCLK periods after
CLKFWDRST is deasserted.
Action
A CLKFWDRST is asserted by the Northbridge.
B Issue a CONNECT special cycle.*
C
Return internal clocks to full speed and assert
PROCRDY
*
The Connect special cycle is only issued after a
processor wake-up event (interrupt or STPCLK#
deassertion) occurs. If the AMD Athlon system bus
is connected so the Northbridge can probe the
processor a Connect special cycle is not issued at
that time (it is only issued after a subsequent
processor wake-up event).
Connect
Disconnect
Pending
Disconnect
Connect
Pending 1
Connect
Pending 2
1
3/A
4/C
5
6/B
2/B
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