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參數(shù)資料
| 型號(hào)： | A0800AMS3C |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 800 MHz, MICROPROCESSOR, CPGA462 |
| 封裝： | STAGGERED, CERAMIC, PGA-453 |
| 文件頁數(shù)： | 7/90頁 |
| 文件大?。?/td> | 1492K |
| 代理商： | A0800AMS3C |
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Chapter 1
Overview
1
23792H—March 2001
AMD Athlon Processor Model 4 Data Sheet
Preliminary Information
1
Overview
The AMD Athlon Processor Model 4 powers the next generation in
computing platforms, delivering compelling performance for
cutting-edge applications and an unprecedented computing
experience.
The AMD Athlon processor with performance-enhancing cache
memory is the latest member of the AMD Athlon family of
processors designed to meet the computation-intensive
requirements of cutting-edge software applications running on
high-performance desktop systems, workstations, and servers.
Delivered in a PGA package and achieving frequencies of
1.333-GHz (1333 MHz), the AMD Athlon processor delivers the
integer, floating-point and 3D multimedia performance for the
most demanding applications running on x86 system platforms.
For cutting-edge software applications, including digital
content creation, digital photo editing, digital video, image
compression, video encoding for streaming over the internet,
sof t DV D, c o mmerc ial 3D mod e li ng, wo rkstati o n-cl ass
computer-aided design (CAD), commercial desktop publishing,
and speech recognition, the AMD Athlon processor delivers
compelling performance. It also offers the scalability and
‘peace-of-mind’ reliability that IT managers and business users
require for enterprise computing.
The AMD Athlon processor features the seventh-generation
microarchitecture with an integrated L2 cache, which supports
the growing processor and system bandwidth requirements of
emerging software, graphics, I/O, and memory technologies.
The AMD Athlon processor's high-speed execution core
includes multiple x86 instruction decoders, a dual-ported
128-Kbyte split level-one (L1) cache, a 256-Kbyte on-chip L2
cache, three independent integer pipelines, three address
calculation pipelines, and a superscalar, fully pipelined,
out-of-order, three-way floating-point engine. The floating-point
engine is capable of delivering superior performance on
numerically complex applications.
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