參數(shù)資料
型號: A1400AMT3C
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA453
封裝: STAGGERED, CERAMIC, PGA-453
文件頁數(shù): 21/90頁
文件大?。?/td> 1497K
代理商: A1400AMT3C
14
Power Management
Chapter 4
AMD Athlon Processor Model 4 Data Sheet
23792I—June 2001
Preliminary Information
3. When the Stop Grant special cycle is received by the
Northbridge
and
no
probe
traffic
is
pending,
the
Northbridge
deasserts
CONNECT,
initiating
a
bus
disconnect to the processor.
4. The processor responds to the Northbridge by deasserting
PROCRDY, acknowledging the bus disconnect request.
5. The Northbridge asserts CLKFWDRST to complete the bus
disconnect sequence.
6. After the processor is disconnected from the bus, the
Northbridge passes the Stop Grant special cycle to the
Southbridge.
Figure 5 shows the signal sequence of events that take the
processor out of the Stop Grant state, reconnect the processor
to the AMD Athlon system bus, and put the processor into the
Working state.
Figure 5. Exiting Stop Grant State/Bus Reconnect Sequence
The following sequence of events removes the processor from
the Stop Grant state and reconnects it to the AMD Athlon
system bus:
1. The Southbridge deasserts STPCLK# in response to a
resume event.
2. When the processor recognizes STPCLK# deassertion, it
asserts PROCRDY, notifying the Northbridge to reconnect
to the bus.
3. The Northbridge asserts CONNECT.
4. The Northbridge finally deasserts CLKFWDRST, which
synchronizes the forwarded clocks between the processor
and the Northbridge.
STPCLK#
PROCRDY
CONNECT
CLKFWDRST
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