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參數(shù)資料
| 型號： | A1400AMT3C |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA453 |
| 封裝： | STAGGERED, CERAMIC, PGA-453 |
| 文件頁數(shù)： | 47/90頁 |
| 文件大?。?/td> | 1497K |
| 代理商： | A1400AMT3C |
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Chapter 8
Signal and Power-Up Requirements
37
23792I—June 2001
AMD Athlon Processor Model 4 Data Sheet
Preliminary Information
3. The system clock (SYSCLK/SYSCLK#) must be running
within specification before PWROK is asserted.
When PWROK is asserted, the processor switches from
driving the internal processor clock grid from the ring
oscillator to driving from the PLL. The reference system
clock should be valid at this time. The system clocks are
guaranteed to be running after 3.3V has been within
specification for 3 milliseconds.
4. PWROK assertion to deassertion of RESET#.
The duration of RESET# assertion during cold boots is
intended to satisfy the time it takes for the PLL to lock with
a less than 1-ns phase error. The processor PLL begins to
run after PWROK is asserted and the internal clock grid is
switched from the ring oscillator to the PLL. The PLL lock
time may take from hundreds of nanoseconds to tens of
microseconds. It is recommended that the minimum time
between PWROK assertion to the deassertion of RESET# be
at least 1.0ms. AMD Southbridges enforce a delay of 1.5 to
2.0 milliseconds between PWRGD (Southbridge version of
PWROK) assertion and NB_RESET# deassertion.
5. PWROK must be monotonic.
The processor should not switch between the ring oscillator
and the PLL after the initial assertion of PWROK.
6. NB_RESET# must be asserted (causing CONNECT to also
assert) before RESET# is deasserted. In practice all
Southbridges enforce this requirement.
If NB_RESET# does not assert until after RESET# has
deasserted, the processor misinterprets the CONNECT
assertion (due to NB_RESET# being asserted) as the
beginning of the SIP transfer (See “Serial Initialization
Packet (SIP) Protocol” on page 38). There must be sufficient
overlap in the resets to ensure that CONNECT is sampled
asserted by the processor before RESET# is deasserted.
Clock Multiplier
Selection (FID[3:0])
When RESET# is deasserted, the Northbridge samples the
FID[3:0] frequency ID from the processor in a chipset-specific
manner. For more information, see “FID[3:0] Pins” on page 63.
The N o rthbridge uses this F ID info rmat io n and other
info rmati on sampled at the deas sertion of RESET# to
determine the correct Serial Initialization Packet (SIP) to send
to the processor for configuration of the AMD system bus for
the clock multiplier processor frequency indicated by the
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